In auto sequence mode, the internal channel sequencer can selectively scan channels from AIN0 through AIN7 in ascending order. To select auto sequence mode, configure SEQ_MODE to 10b in the DEVICE_CFG register using a 3-byte register access. One or more channels among AIN[7:0] can be enabled by configuring the AUTO_SEQ_CFG1 register. By default all analog input channels are enabled. After enabling the desired channels, the sequence can be started by setting SEQ_START to 1b. The ADC auto-increments through the enabled channels after every CS rising edge. When SEQ_START is set to 1b, the SDO-1/SEQSTS pin is at logic 1 as shown in Figure 46 until the last channel conversion frame is complete. After the last enabled channel conversion is complete, channel AIN0 is selected and SDO-1/SEQSTS is in a high-impedance state.
As an example, Figure 47 depicts a timing diagram for when the device is scanning AIN2 and AIN6 in auto sequence mode. When AIN6 is converted, SDO-1/SEQSTS is Hi-Z and AIN0 is selected as the active channel. At the end of sequence, if more conversion frames are launched the device returns valid data corresponding to AIN0.
To use the device in auto sequence mode follow these steps:
To repeat a channel sequence indefinitely, set the AUTO_REPEAT bit in the AUTO_SEQ_CFG2 register to 1b. Figure 48 shows that when the AUTO_REPEAT bit is enabled, the MUX scans through the channels enabled in the AUTO_SEQ_CFG1 register and repeats the sequence after the last channel data are converted.
Figure 48 provides a timing diagram for when the device is scanning AIN2 and AIN6 in auto sequence mode with AUTO_REPEAT = 1b. When AIN6 is converted, AIN2 is selected as the active channel and the device continues scanning through the enabled channels again.
To use the device in auto sequence with the repeat mode enabled follow these steps:
To terminate an ongoing channel sequence set the SEQ_ABORT bit in the SEQ_ABORT register 1. When SEQ_ABORT is set, the auto sequence stops and AIN0 is selected as the active input channel.