The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK speeds and still achieve the required cycle time with a faster response time. Figure 50 shows the ADS816x Interface connections for the minimum number of pins required by the enhanced-SPI interface.
For any data write operation, the host controller can use any of the four legacy, SPI-compatible protocols to configure the device, as described in the Protocols for Configuring the Device section. See the Register Read/Write Operation section for details about the register read or write operation.
For reading ADC conversion data or register data from the device, the enhanced-SPI interface module offers the following options: