The device provides an option to increase the SDO-x bus width from one bit (default, single SDO-x) to two bits (dual SDO-x) when operating with clock re-timer data transfer. In order to operate the device in dual SDO mode, the SDO_WIDTH bit in the SDO_CNTL1 register must be set to 1b. In this mode, the SDO-1/SEQSTS pin functions as SDO-1.
For any particular data transfer, SPI or clock re-timer, the device follows the same timing specifications for single and dual SDO modes. The only difference is that in the dual SDO mode the device requires half as many clock cycles to output the same number of bits when in single SDO mode, thus reducing the minimum required clock frequency for a certain sampling rate of the ADC.