SBAS817C November 2017 – November 2019 ADS8166 , ADS8167 , ADS8168
The ADC starts converting the sampled analog input channel on the CS rising edge and the internal capacitors are switched to the REFP pins as per the successive approximation algorithm. Most of the switching charge required during the conversion process is provided by an external decoupling capacitor CREFP. If the charge lost from CREFP is not replenished before the next CS rising edge, the voltage on the REFP pins is less than VREFP. The subsequent conversion occurs with this different reference voltage, and causes a proportional error in the output code. The internal reference buffer of the device maintains the voltage on the REFP pins within 0.5 LSB of VREFP. All typical characteristics of the device are specified with the internal reference buffer and the specified value of CREFP.
In burst-mode operation, the ADC samples the selected analog input channel for a long duration of time and then performs a burst of conversions. During the sampling time, the sampling capacitor (CS) is connected to the differential input pins and no charge is drawn from the REFP pins. However, during the very first conversion cycle, there is a step change in the current drawn from the REFP pins. This sudden change in load triggers a transient settling response in the reference buffer. For a fixed input voltage, any transient settling error at the end of the conversion cycle results in a change in output codes over the subsequent conversions. The internal reference buffer of the ADS816x, when used with the recommended value of CREFP, keeps the transient settling error at the end of each conversion cycle within 0.5 LSB. Therefore, the device supports burst-mode operation with every conversion result as per the data sheet specifications.
Figure 37 shows the block diagram of the internal reference and reference buffer.
For the minimum ADC input offset error (VOS), set the REF_SEL[2:0] bits to the value closest to VREF (see the OFST_CAL register). The internal reference buffer has a typical gain of 1 V/V with a minimal offset error (V(RO)), and the output of the buffer is available between the REFP and the REFM pins. Set the REF_OFST[4:0] (see the REF_MRG1 register) bits to add or subtract an intentional offset voltage as described in Table 22.
Short the two REFP pins externally. Short the REFM pin to GND externally. Place a decoupling capacitor CREFP between the REFP and the REFM pins as close to the device as possible; see Figure 36. See the Layout section for layout recommendations.