SBAS817C November 2017 – November 2019 ADS8166 , ADS8167 , ADS8168
This device features configuration registers (as described in the Interface and Hardware Configuration Registers section). These devices support the commands listed in Table 8 to access the internal configuration registers.
|B[23:19]||B[18:8]||B[7:0]||COMMAND ACRONYM||COMMAND DESCRIPTION|
|00001||<11-bit address>||<8-bit data>||WR_REG||Write <8-bit data> to the <11-bit address>|
|00010||<11-bit address>||00000000||RD_REG||Read contents from the <11-bit address>|
|00011||<11-bit address>||<8-bit unmasked bits>||SET_BITS||Set <8-bit unmasked bits> from <11-bit address>|
|00100||<11-bit address>||<8-bit unmasked bits>||CLR_BITS||Clear <8-bit unmasked bits> from <11-bit address>|
|Remaining combinations||xxxxxxxxx||xxxxxxxx||Reserved||These commands are reserved and treated by the device as no operation|
The ADS816x supports two types of data transfer operations: data write (the host controller configures the device), and data read (the host controller reads data from the device).
Any data write to the device is always synchronous to the external clock provided on the SCLK pin. The WR_REG command writes the 8-bit data into the 11-bit address specified in the command string. The CLR_BITS command clears the specified bits (identified by 1) at the 11-bit address (without affecting the other bits), and the SET_BITS command sets the specified bits (identified by 1) at the 11-bit address (without affecting the other bits).
Figure 57 shows the digital waveform for register read operation. Register read operation consists of two frames: one frame to initiate a register read and a second frame to read data from the register address provided in the first frame. As shown in Figure 57, the 11-bit register address and the 8-bit dummy data are sent over the SDI pin during the first 24-bit frame with the read command (00010b). When CS goes from low to high, this read command is decoded and the requested register data are available for reading during the next frame. During the second frame, the first eight bits on SDO correspond to the requested register read. During the second frame SDI can be used to initiate another operation or can be set to 0.
Figure 58 shows that for writing data to the register, one 24-bit frame is required. The 24-bit data on SDI consists of a 5-bit write command (00001b), an 11-bit register address, and 8-bit data. The write command is decoded on the CS rising edge and the specified register is updated with the 8-bit data specified during register write operation.