This register configures the protocol for reading data from the device. Write access to this register is disabled on power-up. To enable write access, configure the REG_ACCESS register.
|7||0||R||0b||Reserved bit. Do not write. Read returns 0b.|
|6||OUTDATA_uC_MODE||R/W||0b||Enables the MCU or processor-friendly data interface.
0b = Length of output data is determined by the DATA_OUT_FORMAT field in the DATA_CNTL register.
1b = Length of output data is fixed to 16-bits when the length based on DATA_OUT_FORMAT is ≤ 16 or 32-bits when the length based on DATA_OUT_FORMAT is > 16.
|5||DATA_RIGHT_ALIGNED||R/W||0b||This bit is ignored if OUTDATA_uC_MODE = 0b. When OUTDATA_uC_MODE = 1b:
0b = Data frame is left aligned. The SDOs output the device data bits followed by 0s in a 32-bit output frame.
1b = Data frame is right aligned. The SDOs output 0s followed by device data bits in a 32-bit output frame.
|4||BYTE_INTERLEAVE||R/W||0b||This bit is ignored if OUTDATA_uC_MODE = 0b or SDO_WIDTH = 0b. When OUTDATA_uC_MODE = 1b and SDO_WIDTH = 1b:
0b = Bit mode. SDO-1 outputs (MSB, MSB - 2 ..., LSB + 1) and SDO-0 outputs (MSB - 1, MSB - 3, ..., LSB).
1b = Byte mode. If the total number of bits to be read from the device is N (conversion result, parity, channel ID, and so forth) then SDO-1 outputs 8 MSB bits and SDO-0 outputs (N-8) bits when N ≤16 and SDO-1 outputs 16 MSB bits and SDO-0 outputs (N-16) bits when 16 < N ≤ 32.
|3||0||R||0b||Reserved bit. Do not write. Read returns 0b.|
|2||SDO_WIDTH||R/W||0b||This bit sets the width of the output bus.
0b = Data bits are output only on SDO-0
1b = Data bits are output on SDO-0 (MSB - 1, MSB - 3 ..., LSB) and SDO-1 (MSB, MSB - 2 ..., LSB + 1)
|1-0||SDO_MODE[1:0]||R/W||00b||These bits select the protocol for reading data from the device.
00b = SDO follows the SPI protocol selected in the SDI_CNTL register
01b = Invalid configuration, not supported by the device
10b = Invalid configuration, not supported by the device
11b = SDO follows the Clock Re-Timer Data Transfer section