Figure 101 shows the external amplifier, charge bucket filter, and sample-and-hold circuit at the ADC input for the ADS816x. Having a short background on the conversion process helps to understand the design procedure for selecting the amplifier and RC filter. The conversion process is broken up into two phases: the acquisition phase and the conversion phase. During the acquisition phase the SW switches are closed, and the input signal is stored on the sample-and-hold capacitors, CS1 and CS2. After the acquisition phase, the switches opens and the voltage stored on the capacitors is converted to a digital code by the SAR algorithm. This conversion process depletes the charge on the sample-and-hold capacitors.
During subsequent acquisition cycles, the sample-and-hold capacitor must be charged to the ADC input voltage that can make step changes in the value because each input may be from a different multiplexer channel. For example, if AIN0 is connected to 4 V and AIN1 is connected to 0.5 V, the sample-and-hold capacitor must charge to 4 V for the first acquisition cycle and then must charge to 0.5 V for the second acquisition cycle. When running at high throughput, the acquisition time is small and a wide bandwidth amplifier is required for proper settling at the ADC inputs (minimum acquisition time for the ADS816x is tACQ = 330 ns). The RC filter (RFLT and CFLT) is designed to provide a reservoir of charge that helps rapidly charge the internal sample-and-hold capacitor at the start of the acquisition period. For this reason, the RC filter is sometimes called a charge bucket or charge kickback filter. A method for determining the required amplifier bandwidth and the values of the RC charge bucket filter is provided in this section.
A summary of the equations and an example calculation is provided to determine the amplifier bandwidth and RC charge bucket circuit for the ADS816x assuming a minimum ADC acquisition time is used. Equation 5 finds the amplifier time constant and Equation 6 uses this to computer the amplifiers required unity-gain bandwidth.
The value of CFLT is computed in Equation 10 by taking 20 times the internal sample-and-hold capacitance. The factor of 20 is a rule of thumb that is intended to minimize the droop in voltage on the charge bucket capacitor, CFLT, after the start of the acquisition period. The filter resistor, RFLT, is computed in Equation 11 using the op amp time constant and CFLT. These equations model the system as a first-order system, but in reality the system is a higher order. Consequently, the values may need to be adjusted to optimize performance. This optimization and more details on the math behind the component selection are covered in the ADC Precision Labs training videos.