(At the CS Falling Edge)
|MSB BIT LAUNCH EDGE||SDI_MODE[1:0] BITS||SDO_MODE[1:0] BITS||DIAGRAM|
|SPI-00||Low||Rising||CS falling||00h||00h||Figure 53|
|SPI-01||Low||Falling||1st SCLK rising||01h||00h||Figure 53|
|SPI-10||High||Falling||CS falling||02h||00h||Figure 54|
|SPI-11||High||Rising||1st SCLK falling||03h||00h||Figure 54|
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00 protocol for data read and data write operations. To select a different SPI-compatible protocol for both of the data transfer operations:
The SPI transfer protocol selected by configuring the SDI_MODE[1:0] bits in the SDI_CNTL register determines the data transfer protocol for both write and read operations.
When using any of the SPI-compatible protocols, the READY output remains low throughout the data transfer frame.