SBAS843 September   2017 ADS8588H

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: CONVST Control
    7. 6.7  Timing Requirements: Data Read Operation
    8. 6.8  Timing Requirements: Parallel Data Read Operation, CS and RD Tied Together
    9. 6.9  Timing Requirements: Parallel Data Read Operation, CS and RD Separate
    10. 6.10 Timing Requirements: Serial Data Read Operation
    11. 6.11 Timing Requirements: Byte Mode Data Read Operation
    12. 6.12 Timing Requirements: Oversampling Mode
    13. 6.13 Timing Requirements: Exit Standby Mode
    14. 6.14 Timing Requirements: Exit Shutdown Mode
    15. 6.15 Switching Characteristics: CONVST Control
    16. 6.16 Switching Characteristics: Parallel Data Read Operation, CS and RD Tied Together
    17. 6.17 Switching Characteristics: Parallel Data Read Operation, CS and RD Separate
    18. 6.18 Switching Characteristics: Serial Data Read Operation
    19. 6.19 Switching Characteristics: Byte Mode Data Read Operation
    20. 6.20 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Third-Order, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Digital Filter and Noise
      8. 7.3.8  Reference
        1. 7.3.8.1 Internal Reference
        2. 7.3.8.2 External Reference
        3. 7.3.8.3 Supplying One VREF to Multiple Devices
      9. 7.3.9  ADC Transfer Function
      10. 7.3.10 ADS8588H Device Family Comparison
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RANGE (Input)
        3. 7.4.1.3  STBY (Input)
        4. 7.4.1.4  PAR/SER/BYTE SEL (Input)
        5. 7.4.1.5  CONVSTA, CONVSTB (Input)
        6. 7.4.1.6  RESET (Input)
        7. 7.4.1.7  RD/SCLK (Input)
        8. 7.4.1.8  CS (Input)
        9. 7.4.1.9  OS[2:0]
        10. 7.4.1.10 BUSY (Output)
        11. 7.4.1.11 FRSTDATA (Output)
        12. 7.4.1.12 DB15/BYTE SEL
        13. 7.4.1.13 DB14/HBEN
        14. 7.4.1.14 DB[13:9]
        15. 7.4.1.15 DB8/DOUTB
        16. 7.4.1.16 DB7/DOUTA
        17. 7.4.1.17 DB[6:0]
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Power-Down Modes
          1. 7.4.2.1.1 Standby Mode
          2. 7.4.2.1.2 Shutdown Mode
        2. 7.4.2.2 Conversion Control
          1. 7.4.2.2.1 Simultaneous Sampling on All Input Channels
          2. 7.4.2.2.2 Simultaneous Sampling Two Sets of Input Channels
        3. 7.4.2.3 Data Read Operation
          1. 7.4.2.3.1 Parallel Data Read
          2. 7.4.2.3.2 Parallel Byte Data Read
          3. 7.4.2.3.3 Serial Data Read
          4. 7.4.2.3.4 Data Read During Conversion
        4. 7.4.2.4 Oversampling Mode of Operation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

Layout Guidelines

Figure 89 and Figure 90 illustrate a PCB layout example for the ADS8588H.

  • Partition the PCB into analog and digital sections. Care must be taken to ensure that the analog signals are kept away from the digital lines. This layout helps keep the analog input and reference input signals away from the digital noise. In this layout example, the analog input and reference signals are routed on the left side of the board and the digital connections are routed on the right side of the board.
  • Using a single common ground plane is strongly recommended. For designs requiring a split analog and digital ground planes, the analog and digital ground planes must be at the same potential joined together in close proximity to the device.
  • Power sources to the ADS8588H must be clean and well-bypassed. As a result of dynamic currents during conversion, each AVDD must have a decoupling capacitor to keep the supply voltage stable. Use wide traces or a dedicated analog supply plane to minimize trace inductance and reduce glitches. Using a 1-µF, X7R-grade, 0603-size ceramic capacitor is recommended in close proximity to each analog (AVDD) supply pins. Bypass capacitors for AVDD pins 1 and 48 are located on the top layer; see Figure 89. AVDD supply pins 37 and 38 are connected to bypass capacitors in the bottom layer using an isolated via (1); see Figure 90. A separate via (2) is used to connect the bypass capacitor to the AVDD plane.
  • For decoupling the digital (DVDD) supply pin, a 1-µF, X7R-grade, 0603-size ceramic capacitor is recommended. The DVDD bypass capacitor is located in the bottom layer; see Figure 90.
  • REFCAPA and REFCAPB must be shorted together and decoupled to REFGND using a 10-µF, X7R-grade, 0603-size ceramic capacitor placed in close proximity to the pins of the device. This capacitor is placed on the top layer and directly connected to the device pins. Avoid placing vias between the REFCAPA, REFCAPB pins and the decoupling capacitor.
  • The REFIN/REFOUT pin also must be decoupled to REFGND with a 10-µF, X7R-grade, 0603-size ceramic capacitor if the internal reference of the device is used. The capacitor must be placed on the top layer in close to the device pin. Avoid placing vias between the REFIN/REFOUT pin and the decoupling capacitor.
  • The REGCAP1 and REGCAP2 pins must be decoupled to GND using a separate 1-µF, X7R-grade, 0603-size ceramic capacitor on each pin.
  • All ground pins (AGND) must be connected to the ground plane using short, low-impedance paths and independent vias to the ground plane. Connect REFGND to the common GND plane.
  • For the optional channel input low-pass filters, ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.

Layout Example

Figure 89 and Figure 90 illustrate a recommended layout for the ADS8588H along with proper decoupling and reference capacitor placement and connections.

ADS8588H layout_top_sbas642.gif Figure 89. Top Layer Layout
ADS8588H layout_bottom_sbas642.gif Figure 90. Bottom Layer Layout