SBAS905C November   2019  – July 2020 ADS8686S

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams: Universal
    9. 6.9  Timing Diagrams: Parallel Data Read
    10. 6.10 Timing Diagrams: Serial Data Read
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Programmable, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer
      8. 7.3.8  Digital Filter and Noise
      9. 7.3.9  Reference
        1. 7.3.9.1 Internal Reference
        2. 7.3.9.2 External Reference
        3. 7.3.9.3 Supplying One VREF to Multiple Devices
      10. 7.3.10 ADC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RESET (Input)
        3. 7.4.1.3  SEQEN (Input)
        4. 7.4.1.4  HW_RANGESEL[1:0] (Input)
        5. 7.4.1.5  SER/BYTE/PAR (Input)
        6. 7.4.1.6  DB[3:0] (Input/Output)
        7. 7.4.1.7  DB4/SER1W (Input/Output)
        8. 7.4.1.8  DB5/CRCEN (Input/Output)
        9. 7.4.1.9  DB[7:6] (Input/Output)
        10. 7.4.1.10 DB8 (Input/Output)
        11. 7.4.1.11 DB9/BYTESEL (Input/Output)
        12. 7.4.1.12 DB10/SDI (Input/Output)
        13. 7.4.1.13 DB11/SDOB (Input/Output)
        14. 7.4.1.14 DB12/SDOA (Input/Output)
        15. 7.4.1.15 DB13/OS0 (Input/Output)
        16. 7.4.1.16 DB14/OS1 (Input/Output)
        17. 7.4.1.17 DB15/OS2 (Input/Output)
        18. 7.4.1.18 WR/BURST (Input)
        19. 7.4.1.19 SCLK/RD (Input)
        20. 7.4.1.20 CS (Input)
        21. 7.4.1.21 CHSEL[2:0] (Input)
        22. 7.4.1.22 BUSY (Output)
        23. 7.4.1.23 CONVST (Input)
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Shutdown Mode
        2. 7.4.2.2 Operation Mode
          1. 7.4.2.2.1 Hardware Mode
          2. 7.4.2.2.2 Software Mode
        3. 7.4.2.3 Reset Functionality
        4. 7.4.2.4 Channel Selection
          1. 7.4.2.4.1 Hardware Mode Channel Selection
          2. 7.4.2.4.2 Software Mode Channel Selection
        5. 7.4.2.5 Sequencer
          1. 7.4.2.5.1 Hardware Mode Sequencer
          2. 7.4.2.5.2 Software Mode Sequencer
        6. 7.4.2.6 Burst Sequencer
          1. 7.4.2.6.1 Hardware Mode Burst Sequencer
          2. 7.4.2.6.2 Software Mode Burst Sequencer
        7. 7.4.2.7 Diagnostics
          1. 7.4.2.7.1 Analog Diagnosis
          2. 7.4.2.7.2 Interface Diagnosis: SELF TEST and CRC
    5. 7.5 Programming
      1. 7.5.1 Parallel Interface
        1. 7.5.1.1 Reading Conversion Results
        2. 7.5.1.2 Writing Register Data
        3. 7.5.1.3 Reading Register Data
      2. 7.5.2 Parallel Byte Interface
        1. 7.5.2.1 Reading Conversion Results
        2. 7.5.2.2 Writing Register Data
        3. 7.5.2.3 Reading Register Data
      3. 7.5.3 Serial Interface
        1. 7.5.3.1 Reading Conversion Results
        2. 7.5.3.2 Writing Register Data
        3. 7.5.3.3 Reading Register Data
    6. 7.6 Register Maps
      1. 7.6.1 Page1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 8x2 Channel Data Acquisition System (DAQ) for Power Automation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Input Protection for Electrical Overstress
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 Page1 Registers

Table 7-13 lists the Page1 registers. All register offset addresses not listed in Table 7-13 should be considered as reserved locations and the register contents should not be modified.

Table 7-13 Page1 Registers
ADDRESS ACRONYM SECTION
0x2 CONFIGURATION Section 7.6.1.1
0x3 CHANNEL_SEL Section 7.6.1.2
0x4 RANGE_A1 Section 7.6.1.3
0x5 RANGE_A2 Section 7.6.1.4
0x6 RANGE_B1 Section 7.6.1.5
0x7 RANGE_B2 Section 7.6.1.6
0x8 STATUS Section 7.6.1.7
0xA OVER_RANGE_SETTING_A Section 7.6.1.8
0xB OVER_RANGE_SETTING_B Section 7.6.1.9
0xD LPF_CONFIG Section 7.6.1.10
0x10 Device_ID Section 7.6.1.11
0x20 SEQ_STACK_0 Section 7.6.1.12
0x21 SEQ_STACK_1 Section 7.6.1.13
0x22 SEQ_STACK_2 Section 7.6.1.14
0x23 SEQ_STACK_3 Section 7.6.1.15
0x24 SEQ_STACK_4 Section 7.6.1.16
0x25 SEQ_STACK_5 Section 7.6.1.17
0x26 SEQ_STACK_6 Section 7.6.1.18
0x27 SEQ_STACK_7 Section 7.6.1.19
0x28 SEQ_STACK_8 Section 7.6.1.20
0x29 SEQ_STACK_9 Section 7.6.1.21
0x2A SEQ_STACK_10 Section 7.6.1.22
0x2B SEQ_STACK_11 Section 7.6.1.23
0x2C SEQ_STACK_12 Section 7.6.1.24
0x2D SEQ_STACK_13 Section 7.6.1.25
0x2E SEQ_STACK_14 Section 7.6.1.26
0x2F SEQ_STACK_15 Section 7.6.1.27
0x30 SEQ_STACK_16 Section 7.6.1.28
0x31 SEQ_STACK_17 Section 7.6.1.29
0x32 SEQ_STACK_18 Section 7.6.1.30
0x33 SEQ_STACK_19 Section 7.6.1.31
0x34 SEQ_STACK_20 Section 7.6.1.32
0x35 SEQ_STACK_21 Section 7.6.1.33
0x36 SEQ_STACK_22 Section 7.6.1.34
0x37 SEQ_STACK_23 Section 7.6.1.35
0x38 SEQ_STACK_24 Section 7.6.1.36
0x39 SEQ_STACK_25 Section 7.6.1.37
0x3A SEQ_STACK_26 Section 7.6.1.38
0x3B SEQ_STACK_27 Section 7.6.1.39
0x3C SEQ_STACK_28 Section 7.6.1.40
0x3D SEQ_STACK_29 Section 7.6.1.41
0x3E SEQ_STACK_30 Section 7.6.1.42
0x3F SEQ_STACK_31 Section 7.6.1.43

Complex bit access types are encoded to fit into small table cells. Table 7-14 shows the codes that are used for access types in this section.

Table 7-14 Page1 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

7.6.1.1 CONFIGURATION Register (Address = 0x2) [reset = 0x400]

CONFIGURATION is shown in Figure 7-33 and described in Table 7-15.

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Figure 7-33 CONFIGURATION Register
15 14 13 12 11 10 9 8
W/ R REGADDR[5:0] RESERVED
R/W-0b R/W-10b R-0b
7 6 5 4 3 2 1 0
SDEF BURSTEN SEQEN OSR[2:0] STATUSEN CRCEN
R-0b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b
Table 7-15 CONFIGURATION Register Field Descriptions
Bit Field Type Reset Description
15 W/ R R/W 0b Register read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.
14-9 REGADDR[5:0] R/W 10b Selects this register for read / write operation. Write register address to access this register.
8 RESERVED R 0b Reserved. Reads return 0b.
7 SDEF R 0b Self diagnosis error flag.

0b = Test passed. The ADS8686S has configured itself successfully after power-up.

1b = Test failed. A device reset is required.
6 BURSTEN R/W 0b Burst mode control.

0b = Burst mode is disabled.

1b = Burst mode is enabled.
5 SEQEN R/W 0b Channel sequencer control.

0b = Channel sequencer is disabled.

1b = Channel sequencer is enabled.
4-2 OSR[2:0] R/W 0b Oversampling ratio (OSR) configuration.

0b = OSR disabled.

1b = OSR = 2 samples.

10b = OSR = 4 samples.

11b = OSR = 8 samples.

100b = OSR = 16 samples.

101b = OSR = 32 samples.

110b = OSR = 64 samples.

111b = OSR = 128 samples.
1 STATUSEN R/W 0b Status register output control.

0b = Status register contents are not appended to conversion result.

1b = Status register contents are appended to conversion result.
0 CRCEN R/W 0b Data output CRC control. The STATUSEN and CRCEN bits have identical functionality.

7.6.1.2 CHANNEL_SEL Register (Address = 0x3) [reset = 0x600]

CHANNEL_SEL is shown in Figure 7-34 and described in Table 7-16.

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Figure 7-34 CHANNEL_SEL Register
15 14 13 12 11 10 9 8
W/ R REGADDR[5:0] RESERVED
R/W-0b R/W-11b R-0b
7 6 5 4 3 2 1 0
CHSEL_B[3:0] CHSEL_A[3:0]
R/W-0b R/W-0b
Table 7-16 CHANNEL_SEL Register Field Descriptions
Bit Field Type Reset Description
15 W/ R R/W 0b Register read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.
14-9 REGADDR[5:0] R/W 11b Selects this register for read / write operation. Write register address to access this register.
8 RESERVED R 0b Reserved. Reads return 0b.
7-4 CHSEL_B[3:0] R/W 0b Channel selection control for ADC B.

0b = AIN_0B

1b = AIN_1B

10b = AIN_2B

11b = AIN_3B

100b = AIN_4B

101b = AIN_5B

110b = AIN_6B

111b = AIN_7B

1000b = AVDD

1001b = ALDO

1011b = Fixed digital code 0x5555.
3-0 CHSEL_A[3:0] R/W 0b Channel selection control for ADC A.

0b = AIN_0A

1b = AIN_1A

10b = AIN_2A

11b = AIN_3A

100b = AIN_4A

101b = AIN_5A

110b = AIN_6A

111b = AIN_7A

1000b = AVDD

1001b = ALDO

1011b = Fixed digital code 0xAAAA.

7.6.1.3 RANGE_A1 Register (Address = 0x4) [reset = 0x8FF]

RANGE_A1 is shown in Figure 7-35 and described in Table 7-17.

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Figure 7-35 RANGE_A1 Register
15141312111098
W/ RREGADDR[5:0]RESERVED
R/W-0bR/W-100bR-0b
76543210
AIN_3A[1:0]AIN_2A[1:0]AIN_1A[1:0]AIN_0A[1:0]
R/W-11bR/W-11bR/W-11bR/W-11b
Table 7-17 RANGE_A1 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W100bSelects this register for read / write operation. Write register address to access this register.
8RESERVEDR0bReserved. Reads return 0b.
7-6AIN_3A[1:0]R/W11bChannel AIN_3A voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

5-4AIN_2A[1:0]R/W11bChannel AIN_2A voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

3-2AIN_1A[1:0]R/W11bChannel AIN_1A voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

1-0AIN_0A[1:0]R/W11bChannel AIN_0A voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

7.6.1.4 RANGE_A2 Register (Address = 0x5) [reset = 0xAFF]

RANGE_A2 is shown in Figure 7-36 and described in Table 7-18.

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Figure 7-36 RANGE_A2 Register
15141312111098
W/ RREGADDR[5:0]RESERVED
R/W-0bR/W-101bR-0b
76543210
AIN_7A[1:0]AIN_6A[1:0]AIN_5A[1:0]AIN_4A[1:0]
R/W-11bR/W-11bR/W-11bR/W-11b
Table 7-18 RANGE_A2 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access..

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W101bSelects this register for read / write operation. Write register address to access this register.
8RESERVEDR0bReserved. Reads return 0b.
7-6AIN_7A[1:0]R/W11bChannel AIN_7A voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

5-4AIN_6A[1:0]R/W11bChannel AIN_6A voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

3-2AIN_5A[1:0]R/W11bChannel AIN_5A voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

1-0AIN_4A[1:0]R/W11bChannel AIN_4A voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

7.6.1.5 RANGE_B1 Register (Address = 0x6) [reset = 0xCFF]

RANGE_B1 is shown in Figure 7-37 and described in Table 7-19.

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Figure 7-37 RANGE_B1 Register
15141312111098
W/ RREGADDR[5:0]RESERVED
R/W-0bR/W-110bR-0b
76543210
AIN_3B[1:0]AIN_2B[1:0]AIN_1B[1:0]AIN_0B[1:0]
R/W-11bR/W-11bR/W-11bR/W-11b
Table 7-19 RANGE_B1 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W110bSelects this register for read / write operation. Write register address to access this register.
8RESERVEDR0bReserved. Reads return 0b.
7-6AIN_3B[1:0]R/W11bChannel AIN_3B voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

5-4AIN_2B[1:0]R/W11bChannel AIN_2B voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

3-2AIN_1B[1:0]R/W11bChannel AIN_1B voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

1-0AIN_0B[1:0]R/W11bChannel AIN_0B voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

7.6.1.6 RANGE_B2 Register (Address = 0x7) [reset = 0xEFF]

RANGE_B2 is shown in Figure 7-38 and described in Table 7-20.

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Figure 7-38 RANGE_B2 Register
15141312111098
W/ RREGADDR[5:0]RESERVED
R/W-0bR/W-111bR-0b
76543210
AIN_7B[1:0]AIN_6B[1:0]AIN_5B[1:0]AIN_4B[1:0]
R/W-11bR/W-11bR/W-11bR/W-11b
Table 7-20 RANGE_B2 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W111bSelects this register for read / write operation. Write register address to access this register.
8RESERVEDR0bReserved. Reads return 0b.
7-6AIN_7B[1:0]R/W11bChannel AIN_7B voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

5-4AIN_6B[1:0]R/W11bChannel AIN_6B voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = input Range = ± 10 V.

3-2AIN_5B[1:0]R/W11bChannel AIN_5B voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = Input Range = ± 10 V.

1-0AIN_4B[1:0]R/W11bChannel AIN_4B voltage range selection.

0b = Input Range = ± 10 V.

1b = Input Range = ± 2.5 V.

10b = Input Range = ± 5 V.

11b = input Range = ± 10 V.

7.6.1.7 STATUS Register (Address = 0x8) [reset = 0x0]

STATUS is shown in Figure 7-39 and described in Table 7-21.

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Figure 7-39 STATUS Register
15141312111098
CHSEL_A_ID[3:0]CHSEL_B_ID[3:0]
R-0bR-0b
76543210
CRC[7:0]
R-0b
Table 7-21 STATUS Register Field Descriptions
BitFieldTypeResetDescription
15-12CHSEL_A_ID[3:0]R0bChannel index for the last converted channel using ADC A. Refer to register 0x03 CHSEL_A description to decode channel index.
11-8CHSEL_B_ID[3:0]R0bChannel index for the last converted channel using ADC B. Refer to register 0x03 CHSEL_B description to decode channel index.
7-0CRC[7:0]R0b8-bit CRC computation result. Refer to CRC section for further details.

7.6.1.8 OVER_RANGE_SETTING_A Register (Address = 0xA) [reset = 0x1400]

OVER_RANGE_SETTING_A is shown in Figure 7-40 and described in Table 7-22.

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Figure 7-40 OVER_RANGE_SETTING_A Register
15141312111098
W/ RREGADDR[5:0]RESERVED
R/W-0bR/W-1010bR-0b
76543210
AIN_7A_OVER_RANGEAIN_6A_OVER_RANGEAIN_5A_OVER_RANGEAIN_4A_OVER_RANGEAIN_3A_OVER_RANGEAIN_2A_OVER_RANGEAIN_1A_OVER_RANGEAIN_0A_OVER_RANGE
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-22 OVER_RANGE_SETTING_A Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W1010bSelects this register for read / write operation. Write register address to access this register.
8RESERVEDR0bReserved. Reads return 0b.
7AIN_7A_OVER_RANGER/W0bAIN_7A over range control.

0b = Channel AIN_7A range as programmed in register 0x05.

1b = Enable 20% Overrange for Channel AIN_7A range set as programmed in register 0x05.

6AIN_6A_OVER_RANGER/W0bAIN_6A over range control.

0b = Channel AIN_6A range as programmed in register 0x05.

1b = Enable 20% Overrange for Channel AIN_6A range set as programmed in register 0x05.

5AIN_5A_OVER_RANGER/W0bAIN_5A over range control.

0b = Channel AIN_5A range as programmed in register 0x05.

1b = Enable 20% Overrange for Channel AIN_5A range set as programmed in register 0x05.

4AIN_4A_OVER_RANGER/W0bAIN_4A over range control.

0b = Channel AIN_4A range as programmed in register 0x05.

1b = Enable 20% Overrange for Channel AIN_4A range set as programmed in register 0x05.

3AIN_3A_OVER_RANGER/W0bAIN_3A over range control.

0b = Channel AIN_3A range as programmed in register 0x04.

1b = Enable 20% Overrange for Channel AIN_3A range set as programmed in register 0x04.

2AIN_2A_OVER_RANGER/W0bAIN_2A over range control.

0b = Channel AIN_2A range as programmed in register 0x04.

1b = Enable 20% Overrange for Channel AIN_2A range set as programmed in register 0x04.

1AIN_1A_OVER_RANGER/W0bAIN_1A over range control

0b = Channel AIN_1A range as programmed in register 0x04

1b = Enable 20% Overrange for Channel AIN_1A range set as programmed in register 0x04

0AIN_0A_OVER_RANGER/W0bAIN_0A over range control.

0b = Channel AIN_0A range as programmed in register 0x04.

1b = Enable 20% Overrange for Channel AIN_0A range set as programmed in register 0x04.

7.6.1.9 OVER_RANGE_SETTING_B Register (Address = 0xB) [reset = 0x1600]

OVER_RANGE_SETTING_B is shown in Figure 7-41 and described in Table 7-23.

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Figure 7-41 OVER_RANGE_SETTING_B Register
15141312111098
W/ RREGADDR[5:0]RESERVED
R/W-0bR/W-1011bR-0b
76543210
AIN_7B_OVER_RANGEAIN_6B_OVER_RANGEAIN_5B_OVER_RANGEAIN_4B_OVER_RANGEAIN_3B_OVER_RANGEAIN_2B_OVER_RANGEAIN_1B_OVER_RANGEAIN_0B_OVER_RANGE
R/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0bR/W-0b
Table 7-23 OVER_RANGE_SETTING_B Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W1011bSelects this register for read / write operation. Write register address to access this register.
8RESERVEDR0bReserved. Reads return 0b.
7AIN_7B_OVER_RANGER/W0bAIN_7B over range control.

0b = Channel AIN_7B range as programmed in register 0x07.

1b = Enable 20% Overrange for Channel AIN_7B range set as programmed in register 0x07.

6AIN_6B_OVER_RANGER/W0bAIN_6B over range control.

0b = Channel AIN_6B range as programmed in register 0x07.

1b = Enable 20% Overrange for Channel AIN_6B range set as programmed in register 0x07.

5AIN_5B_OVER_RANGER/W0bAIN_5B over range control.

0b = Channel AIN_5B range as programmed in register 0x07.

1b = Enable 20% Overrange for Channel AIN_5B range set as programmed in register 0x07.

4AIN_4B_OVER_RANGER/W0bAIN_4B over range control.

0b = Channel AIN_4B range as programmed in register 0x07.

1b = Enable 20% Overrange for Channel AIN_4B range set as programmed in register 0x07.

3AIN_3B_OVER_RANGER/W0bAIN_3B over range control

0b = Channel AIN_3B range as programmed in register 0x06

1b = Enable 20% Overrange for Channel AIN_3B range set as programmed in register 0x06

2AIN_2B_OVER_RANGER/W0bAIN_2B over range control.

0b = Channel AIN_2B range as programmed in register 0x06.

1b = Enable 20% Overrange for Channel AIN_2B range set as programmed in register 0x06.

1AIN_1B_OVER_RANGER/W0bAIN_1B over range control.

0b = Channel AIN_1B range as programmed in register 0x06.

1b = Enable 20% Overrange for Channel AIN_1B range set as programmed in register 0x06.

0AIN_0B_OVER_RANGER/W0bAIN_0B over range control.

0b = Channel AIN_0B range as programmed in register 0x06.

1b = Enable 20% Overrange for Channel AIN_0B range set as programmed in register 0x06.

7.6.1.10 LPF_CONFIG Register (Address = 0xD) [reset = 0x1A00]

LPF_CONFIG is shown in Figure 7-42 and described in Table 7-24.

Return to the Summary Table.

Figure 7-42 LPF_CONFIG Register
15141312111098
W/ RREGADDR[5:0]RESERVED
R/W-0bR/W-1101bR-0b
76543210
RESERVEDLPF_CONFIG[1:0]
R-0bR/W-0b
Table 7-24 LPF_CONFIG Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W1101bSelects this register for read / write operation. Write register address to access this register.
8-2RESERVEDR0bReserved. Reads return 0b.
1-0LPF_CONFIG[1:0]R/W0bAnalog low pass filter configuration control. The setting is applied to input channels.

0b = LPF cutoff frequency = 39 kHz

1b = LPF cutoff frequency = 15 kHz

10b = LPF cutoff frequency = 376 kHz

7.6.1.11 Device_ID Register (Address = 0x10) [reset = 0x2002]

Device_ID is shown in Figure 7-43 and described in Table 7-25.

Return to the Summary Table.

Figure 7-43 Device_ID Register
15141312111098
W/ RREGADDR[5:0]RESERVED
R/W-0bR/W-10000bR-0b
76543210
RESERVEDDEVICE_ID[1:0]
R-0bR-10b
Table 7-25 Device_ID Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W10000bSelects this register for read / write operation. Write register address to access this register.
8-2RESERVEDR0b
1-0DEVICE_ID[1:0]R10bDevice identification register.

7.6.1.12 SEQ_STACK_0 Register (Address = 0x20) [reset = 0x4000]

SEQ_STACK_0 is shown in Figure 7-44 and described in Table 7-26.

Return to the Summary Table.

Figure 7-44 SEQ_STACK_0 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-100000bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-26 SEQ_STACK_0 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W100000bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.13 SEQ_STACK_1 Register (Address = 0x21) [reset = 0x4211]

SEQ_STACK_1 is shown in Figure 7-45 and described in Table 7-27.

Return to the Summary Table.

Figure 7-45 SEQ_STACK_1 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-100001bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-1bR/W-1b
Table 7-27 SEQ_STACK_1 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W100001bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W1bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W1bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.14 SEQ_STACK_2 Register (Address = 0x22) [reset = 0x4422]

SEQ_STACK_2 is shown in Figure 7-46 and described in Table 7-28.

Return to the Summary Table.

Figure 7-46 SEQ_STACK_2 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-100010bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-10bR/W-10b
Table 7-28 SEQ_STACK_2 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W100010bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W10bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W10bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.15 SEQ_STACK_3 Register (Address = 0x23) [reset = 0x4633]

SEQ_STACK_3 is shown in Figure 7-47 and described in Table 7-29.

Return to the Summary Table.

Figure 7-47 SEQ_STACK_3 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-100011bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-11bR/W-11b
Table 7-29 SEQ_STACK_3 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W100011bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W11bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W11bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.16 SEQ_STACK_4 Register (Address = 0x24) [reset = 0x4844]

SEQ_STACK_4 is shown in Figure 7-48 and described in Table 7-30.

Return to the Summary Table.

Figure 7-48 SEQ_STACK_4 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-100100bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-100bR/W-100b
Table 7-30 SEQ_STACK_4 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W100100bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W100bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W100bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.17 SEQ_STACK_5 Register (Address = 0x25) [reset = 0x4A55]

SEQ_STACK_5 is shown in Figure 7-49 and described in Table 7-31.

Return to the Summary Table.

Figure 7-49 SEQ_STACK_5 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-100101bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-101bR/W-101b
Table 7-31 SEQ_STACK_5 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W100101bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W101bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W101bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.18 SEQ_STACK_6 Register (Address = 0x26) [reset = 0x4C66]

SEQ_STACK_6 is shown in Figure 7-50 and described in Table 7-32.

Return to the Summary Table.

Figure 7-50 SEQ_STACK_6 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-100110bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-110bR/W-110b
Table 7-32 SEQ_STACK_6 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W100110bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W110bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W110bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.19 SEQ_STACK_7 Register (Address = 0x27) [reset = 0x4F77]

SEQ_STACK_7 is shown in Figure 7-51 and described in Table 7-33.

Return to the Summary Table.

Figure 7-51 SEQ_STACK_7 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-100111bR/W-1b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-111bR/W-111b
Table 7-33 SEQ_STACK_7 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W100111bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W1bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W111bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W111bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.20 SEQ_STACK_8 Register (Address = 0x28) [reset = 0x5000]

SEQ_STACK_8 is shown in Figure 7-52 and described in Table 7-34.

Return to the Summary Table.

Figure 7-52 SEQ_STACK_8 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-101000bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-34 SEQ_STACK_8 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W101000bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.21 SEQ_STACK_9 Register (Address = 0x29) [reset = 0x5200]

SEQ_STACK_9 is shown in Figure 7-53 and described in Table 7-35.

Return to the Summary Table.

Figure 7-53 SEQ_STACK_9 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-101001bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-35 SEQ_STACK_9 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W101001bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.22 SEQ_STACK_10 Register (Address = 0x2A) [reset = 0x5400]

SEQ_STACK_10 is shown in Figure 7-54 and described in Table 7-36.

Return to the Summary Table.

Figure 7-54 SEQ_STACK_10 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-101010bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-36 SEQ_STACK_10 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W101010bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.23 SEQ_STACK_11 Register (Address = 0x2B) [reset = 0x5600]

SEQ_STACK_11 is shown in Figure 7-55 and described in Table 7-37.

Return to the Summary Table.

Figure 7-55 SEQ_STACK_11 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-101011bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-37 SEQ_STACK_11 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W101011bSelects this register for read / write operation Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.24 SEQ_STACK_12 Register (Address = 0x2C) [reset = 0x5800]

SEQ_STACK_12 is shown in Figure 7-56 and described in Table 7-38.

Return to the Summary Table.

Figure 7-56 SEQ_STACK_12 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-101100bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-38 SEQ_STACK_12 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W101100bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.25 SEQ_STACK_13 Register (Address = 0x2D) [reset = 0x5A00]

SEQ_STACK_13 is shown in Figure 7-57 and described in Table 7-39.

Return to the Summary Table.

Figure 7-57 SEQ_STACK_13 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-101101bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-39 SEQ_STACK_13 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W101101bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.26 SEQ_STACK_14 Register (Address = 0x2E) [reset = 0x5C00]

SEQ_STACK_14 is shown in Figure 7-58 and described in Table 7-40.

Return to the Summary Table.

Figure 7-58 SEQ_STACK_14 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-101110bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-40 SEQ_STACK_14 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W101110bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.27 SEQ_STACK_15 Register (Address = 0x2F) [reset = 0x5E00]

SEQ_STACK_15 is shown in Figure 7-59 and described in Table 7-41.

Return to the Summary Table.

Figure 7-59 SEQ_STACK_15 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-101111bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-41 SEQ_STACK_15 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W101111bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.28 SEQ_STACK_16 Register (Address = 0x30) [reset = 0x6000]

SEQ_STACK_16 is shown in Figure 7-60 and described in Table 7-42.

Return to the Summary Table.

Figure 7-60 SEQ_STACK_16 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-110000bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-42 SEQ_STACK_16 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W110000bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.29 SEQ_STACK_17 Register (Address = 0x31) [reset = 0x6200]

SEQ_STACK_17 is shown in Figure 7-61 and described in Table 7-43.

Return to the Summary Table.

Figure 7-61 SEQ_STACK_17 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-110001bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-43 SEQ_STACK_17 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W110001bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.30 SEQ_STACK_18 Register (Address = 0x32) [reset = 0x6400]

SEQ_STACK_18 is shown in Figure 7-62 and described in Table 7-44.

Return to the Summary Table.

Figure 7-62 SEQ_STACK_18 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-110010bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-44 SEQ_STACK_18 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W110010bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.31 SEQ_STACK_19 Register (Address = 0x33) [reset = 0x6600]

SEQ_STACK_19 is shown in Figure 7-63 and described in Table 7-45.

Return to the Summary Table.

Figure 7-63 SEQ_STACK_19 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-110011bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-45 SEQ_STACK_19 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W110011bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.32 SEQ_STACK_20 Register (Address = 0x34) [reset = 0x6800]

SEQ_STACK_20 is shown in Figure 7-64 and described in Table 7-46.

Return to the Summary Table.

Figure 7-64 SEQ_STACK_20 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-110100bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-46 SEQ_STACK_20 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W110100bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.33 SEQ_STACK_21 Register (Address = 0x35) [reset = 0x6A00]

SEQ_STACK_21 is shown in Figure 7-65 and described in Table 7-47.

Return to the Summary Table.

Figure 7-65 SEQ_STACK_21 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-110101bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-47 SEQ_STACK_21 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W110101bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.34 SEQ_STACK_22 Register (Address = 0x36) [reset = 0x6C00]

SEQ_STACK_22 is shown in Figure 7-66 and described in Table 7-48.

Return to the Summary Table.

Figure 7-66 SEQ_STACK_22 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-110110bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-48 SEQ_STACK_22 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W110110bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.35 SEQ_STACK_23 Register (Address = 0x37) [reset = 0x6E00]

SEQ_STACK_23 is shown in Figure 7-67 and described in Table 7-49.

Return to the Summary Table.

Figure 7-67 SEQ_STACK_23 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-110111bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-49 SEQ_STACK_23 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W110111bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.36 SEQ_STACK_24 Register (Address = 0x38) [reset = 0x7000]

SEQ_STACK_24 is shown in Figure 7-68 and described in Table 7-50.

Return to the Summary Table.

Figure 7-68 SEQ_STACK_24 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-111000bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-50 SEQ_STACK_24 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W111000bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.37 SEQ_STACK_25 Register (Address = 0x39) [reset = 0x7200]

SEQ_STACK_25 is shown in Figure 7-69 and described in Table 7-51.

Return to the Summary Table.

Figure 7-69 SEQ_STACK_25 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-111001bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-51 SEQ_STACK_25 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W111001bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.38 SEQ_STACK_26 Register (Address = 0x3A) [reset = 0x7400]

SEQ_STACK_26 is shown in Figure 7-70 and described in Table 7-52.

Return to the Summary Table.

Figure 7-70 SEQ_STACK_26 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-111010bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-52 SEQ_STACK_26 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W111010bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.39 SEQ_STACK_27 Register (Address = 0x3B) [reset = 0x7600]

SEQ_STACK_27 is shown in Figure 7-71 and described in Table 7-53.

Return to the Summary Table.

Figure 7-71 SEQ_STACK_27 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-111011bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-53 SEQ_STACK_27 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W111011bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.40 SEQ_STACK_28 Register (Address = 0x3C) [reset = 0x7800]

SEQ_STACK_28 is shown in Figure 7-72 and described in Table 7-54.

Return to the Summary Table.

Figure 7-72 SEQ_STACK_28 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-111100bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-54 SEQ_STACK_28 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W111100bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.41 SEQ_STACK_29 Register (Address = 0x3D) [reset = 0x7A00]

SEQ_STACK_29 is shown in Figure 7-73 and described in Table 7-55.

Return to the Summary Table.

Figure 7-73 SEQ_STACK_29 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-111101bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-55 SEQ_STACK_29 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W111101bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.

7.6.1.42 SEQ_STACK_30 Register (Address = 0x3E) [reset = 0x7C00]

SEQ_STACK_30 is shown in Figure 7-74 and described in Table 7-56.

Return to the Summary Table.

Figure 7-74 SEQ_STACK_30 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-111110bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-56 SEQ_STACK_30 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W111110bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting

7.6.1.43 SEQ_STACK_31 Register (Address = 0x3F) [reset = 0x7E00]

SEQ_STACK_31 is shown in Figure 7-75 and described in Table 7-57.

Return to the Summary Table.

Figure 7-75 SEQ_STACK_31 Register
15141312111098
W/ RREGADDR[5:0]SSREN
R/W-0bR/W-111111bR/W-0b
76543210
CHSEL_B[3:0]CHSEL_A[3:0]
R/W-0bR/W-0b
Table 7-57 SEQ_STACK_31 Register Field Descriptions
BitFieldTypeResetDescription
15W/ RR/W0bRegister read write access.

0b = Selects the register for read access.

1b = Selects the register for write access.

14-9REGADDR[5:0]R/W111111bSelects this register for read / write operation. Write register address to access this register.
8SSRENR/W0bSequence stack return control.

0b = Move to next stack register after ongoing conversion complete.

1b = Move to first stack register after ongoing conversion complete.

7-4CHSEL_B[3:0]R/W0bChannel selection control for ADC B. Refer to register 0x03 CHSEL_B field description for individual selection setting.
3-0CHSEL_A[3:0]R/W0bChannel selection control for ADC A. Refer to register 0x03 CHSEL_A field description for individual selection setting.