A typical connection diagram showing multiple devices in a daisy-chain topology is shown in Figure 87.
The CONVST, CS, and SCLK inputs of all devices are connected together and controlled by a single CONVST, CS, and SCLK pin of the host controller, respectively. The SDI input pin of the first device in the chain (Device 1) is connected to the SDO pin of the host controller, the SDO-0 output pin of Device 1 is connected to the SDI input pin of Device 2, and so on. The SDO-0 output pin of the last device in the chain (Device N) is connected to the SDI pin of the host controller.
To operate multiple devices in a daisy-chain topology, the host controller sets the configuration registers in each device with identical values and operates with any of the legacy, SPI-compatible protocols for data-read and data-write operations (SDO_CNT[7:0] = 00h or 01h). With these configurations settings, the 22-bit ODR and 22-bit IDR registers in each device collapse to form a single, 22-bit unified shift register (USR) per device, as shown in Figure 88.
All devices in the daisy-chain topology sample the respective device analog input signals on the CONVST rising edge. The data transfer frame starts with a CS falling edge. On each SCLK launch edge, every device in the chain shifts out the MSB of the respective USR on to the respective SDO-0 pin. On every SCLK capture edge, each device in the chain shifts in data received on the respective SDI pin as the LSB bit of the respective USR. Therefore, in a daisy-chain configuration, the host controller receives the data of Device N, followed by the data of Device N – 1, and so on (MSB-first). On the CS rising edge, each device decodes the contents in the respective USR, and takes appropriate action.
A typical timing diagram for three devices connected in daisy-chain topology using the SPI-00-S protocol is shown in Figure 89.
In daisy-chain topology, the overall throughput of the system is proportionally reduced as more devices are connected in the daisy-chain.
For N devices connected in daisy-chain topology, an optimal data transfer frame must contain 22 × N SCLK capture edges. For a longer data transfer frame (number of SCLK in the frame > 22 × N), the host controller must appropriately align the configuration data for each device before bringing CS high. A shorter data transfer frame (number of SCLK in the frame < 22 × N) might result in an erroneous device configuration, and must be avoided.