SLVSIN3 May   2025 ADS9117 , ADS9118 , ADS9119

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Thermal Information
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics: All Devices
    10. 6.10 Typical Characteristics: ADS9119
    11. 6.11 Typical Characteristics: ADS9118
    12. 6.12 Typical Characteristics: ADS9117
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs
      2. 7.3.2 Analog Input Bandwidth
      3. 7.3.3 ADC Transfer Function
      4. 7.3.4 Reference Voltage
      5. 7.3.5 Temperature Sensor
      6. 7.3.6 Data Averaging
      7. 7.3.7 Digital Down Converter
      8. 7.3.8 Data Interface
        1. 7.3.8.1 Data Frame Width
        2. 7.3.8.2 ADC Output Data Randomizer
        3. 7.3.8.3 Synchronizing Multiple ADCs
        4. 7.3.8.4 Test Patterns for Data Interface
          1. 7.3.8.4.1 Fixed Pattern
          2. 7.3.8.4.2 Alternating Test Pattern
          3. 7.3.8.4.3 Digital Ramp
      9. 7.3.9 ADC Sampling Clock Input
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
      2. 7.4.2 Power-Down Options
      3. 7.4.3 Normal Operation
      4. 7.4.4 Initialization Sequence
    5. 7.5 Programming
      1. 7.5.1 Register Write
      2. 7.5.2 Register Read
      3. 7.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 7.5.3.1 Register Write With Daisy-Chain
        2. 7.5.3.2 Register Read With Daisy-Chain
  9. 8 Register Map
    1. 8.1 Register Bank 0
    2. 8.2 Register Bank 1
    3. 8.3 Register Bank 2
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Data Acquisition (DAQ) Circuit for a ≤20kHz Input Signal Bandwidth
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Data Acquisition (DAQ) Circuit for a ≤100kHz Input Signal Bandwidth
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Application Curves
      3. 9.2.3 Data Acquisition (DAQ) Circuit for a ≤1MHz Input Signal Bandwidth
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

at AVDD_5V = 4.75V to 5.25V, VDD_1V8 = 1.75V to 1.85V, internal VREF = 4.096V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
IB Input bias current 0.1 nA
Input bias current thermal drift TA = 0°C to 70°C 0.02 nA/℃
TA = –40°C to 125°C 0.1
DC PERFORMANCE
Resolution No missing codes 18 Bits
DNL Differential nonlinearity –0.9 ±0.4 0.9 LSB
INL Integral nonlinearity TA = 0°C to 70°C, all devices –1.125 ±0.8 1.125 LSB
TA = –40°C to 125°C, all devices –1.9 ±0.8 1.9 LSB
V(OS) Input offset error(1) ±40 LSB
dVOS/dT Input offset error thermal drift(1) 0.25 1 ppm/°C
GE Gain error(1) –0.05 ±0.01 0.05 %FSR
dGE/dT Gain error thermal drift(1) 0.5 2 ppm/°C
AC PERFORMANCE
SINAD Signal-to-noise + distortion ratio fIN = 2kHz 93 95.4 dB
fIN = 1MHz 94.3
SNR Signal-to-noise ratio fIN = 2kHz 93.3 95.5 dBFS
fIN = 1MHz 94.9
THD Total harmonic distortion fIN = 2kHz, ADS9117 and ADS9118 –120 dB
fIN = 2kHz, ADS9119 at 20MSPS –118
fIN = 1MHz, all devices –104
SFDR Spurious-free dynamic range fIN = 2kHz 118 dB
fIN = 1MHz 104
Isolation crosstalk fIN = 2kHz 120 dB
Aperture jitter SIngle-ended CMOS clock on SMPL_CLKP 0.3 psRMS
Differential LVDS sampling clock  0.8
BW Input Bandwidth (–3dB) ADS9119 90 MHz
ADS9118 90
ADS9117 45
INTERNAL REFERENCE
VREF(2) Voltage on REFIO pin
(configured as output)		 1µF capacitor on REFIO pin, TA = 25°C 4.092 4.096 4.1 V
Reference temperature drift 6 20 ppm/°C
COMMON-MODE OUTPUT BUFFER
VCMOUT Common-mode output voltage ADS9119 2.2 2.460 2.65 V
ADS9118 2.2 2.410 2.65
ADS9117 2.2 2.385 2.65
Output current drive 0 5 μA
LVDS RECEIVER (SMPL_CLK)
VTH High-level input voltage (P – M) AC coupled 100 mV
DC coupled 300
VTL Low-level input voltage (P – M) AC coupled –100 mV
DC coupled –300
VICM Input common-mode voltage 0.5 1.2 1.4 V
LVDS OUTPUT (CLKOUT, DOUTA, and DOUTB)
VODIFF Differential output voltage RL = 100Ω 200 350 500 mV
VOCM Output common-mode voltage RL = 100Ω 0.88 1.1 1.32 V
CMOS INPUTS (CS, SCLK, and SDI)
VIL Input low logic level –0.1 0.5 V
VIH Input high logic level 1.3 VDD_1V8 V
CMOS OUTPUT (SDO)
VOL Output low logic level IOL = 200µA sink 0 0.4 V
VOH Output high logic level IOH = 200µA source 1.4 VDD_1V8 V
POWER SUPPLY
IAVDD_5V Supply current from AVDD_5V At 20MSPS throughput (ADS9119) 31 34 mA
At 10MSPS throughput (ADS9118) 17 21
At 5MSPS throughput (ADS9117) 10 13
Power-down 2
IVDD_1V8 Supply current from VDD_1V8 At 20MSPS throughput (ADS9119) 66 69 mA
At 10MSPS throughput (ADS9118) 45 47
At 5MSPS throughput (ADS9117) 37.5 41

Power-down

 2
(1) These specifications include full temperature range variation but not the error contribution from internal reference.
(2) Does not include the variation in voltage resulting from solder shift effects.