SBAS876C August   2018  – June 2019 ADS9224R , ADS9234R

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADS92x4R
    6. 6.6  Electrical Characteristics: ADS9224R
    7. 6.7  Electrical Characteristics: ADS9234R
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics: ADS9224R
    11. 6.11 Typical Characteristics: ADS9234R
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Modules
        1. 7.3.1.1 Analog Input With Sample-and-Hold
        2. 7.3.1.2 ADC Transfer Function
      2. 7.3.2 Internal Reference Voltage
      3. 7.3.3 Reference Buffers
      4. 7.3.4 REFby2 Buffer
      5. 7.3.5 Data Averaging
        1. 7.3.5.1 Averaging of Two Samples
        2. 7.3.5.2 Averaging of Four Samples
    4. 7.4 Device Functional Modes
      1. 7.4.1 ACQ State
      2. 7.4.2 CNV State
      3. 7.4.3 Reset or Power-Down
        1. 7.4.3.1 Reset
        2. 7.4.3.2 Power-Down
      4. 7.4.4 Conversion Control and Data Transfer Frame
        1. 7.4.4.1 Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)
        2. 7.4.4.2 Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)
    5. 7.5 READY/STROBE Output
      1. 7.5.1 READY Output
      2. 7.5.2 STROBE Output
    6. 7.6 Programming
      1. 7.6.1 Output Data Word
      2. 7.6.2 Data Transfer Protocols
        1. 7.6.2.1 Protocols for Reading From the Device
          1. 7.6.2.1.1 Legacy, SPI-Compatible Protocols (SPI-xy-S-SDR)
          2. 7.6.2.1.2 SPI-Compatible Protocols With Bus Width Options and Single Data Rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)
          3. 7.6.2.1.3 SPI-Compatible Protocols With Bus Width Options and Double Data Rate (SPI-x1-S-DDR, SPI-x1-D-DDR, SPI-x1-Q-DDR)
          4. 7.6.2.1.4 Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-DDR)
          5. 7.6.2.1.5 Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR)
        2. 7.6.2.2 Device Setup
          1. 7.6.2.2.1 Single Device: All Enhanced-SPI Options
          2. 7.6.2.2.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.6.2.3 Protocols for Configuring the Device
      3. 7.6.3 Reading and Writing Registers
    7. 7.7 Register Maps
      1. 7.7.1 ADS92x4R Registers
        1. 7.7.1.1 DEVICE_STATUS Register (Offset = 0h) [reset = 0h]
          1. Table 12. DEVICE_STATUS Register Field Descriptions
        2. 7.7.1.2 POWER_DOWN_CFG Register (Offset = 1h) [reset = 0h]
          1. Table 13. POWER_DOWN_CFG Register Field Descriptions
        3. 7.7.1.3 PROTOCOL_CFG Register (Offset = 2h) [reset = 0h]
          1. Table 14. PROTOCOL_CFG Register Field Descriptions
        4. 7.7.1.4 BUS_WIDTH Register (Offset = 3h) [reset = 0h]
          1. Table 15. BUS_WIDTH Register Field Descriptions
        5. 7.7.1.5 CRT_CFG Register (Offset = 4h) [reset = 0h]
          1. Table 16. CRT_CFG Register Field Descriptions
        6. 7.7.1.6 OUTPUT_DATA_WORD_CFG Register (Offset = 5h) [reset = 0h]
          1. Table 17. OUTPUT_DATA_WORD_CFG Register Field Descriptions
        7. 7.7.1.7 DATA_AVG_CFG Register (Offset = 6h) [reset = 0h]
          1. Table 18. DATA_AVG_CFG Register Field Descriptions
        8. 7.7.1.8 REFBY2_OFFSET Register (Offset = 7h) [reset = 0h]
          1. Table 19. REFBY2_OFFSET Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
        1. 8.1.1.1 Charge-Kickback Filter
      2. 8.1.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.3 Reading and Writing Registers

To read a register or write into a register, the host must provide a 16-bit command frame C[15:0] on SDI. A command frame consists of an OPCODE[3:0], ADDRESS[3:0], and DATA[7:0]. The host must keep the CONVST signal high for reading and writing the registers. Figure 70 shows the command frame. Table 9 provides the details of commands for reading and writing registers.

ADS9224R ADS9234R command_frame_SBAS876.gifFigure 70. Command Frame C[15:0]

Table 9. Commands for Reading and Writing Registers

OPCODE[3:0] DESCRIPTION ADDRESS[3:0] DATA[7:0]
0000 NOP0 Command for conversion control and reading conversion results N/A N/A
0001 WRITE Command for writing registers 4-bit register address 8-bit register data
0010 READ(1) Command for reading registers 4-bit register address 00h or FFh
0101 Set bit Command for setting specific bits in a register without changing the other bits 4-bit register address Bits with values of 1 in DATA are set and bits with values of 0 in register data are not changed.
0110 Clear bit Command for clearing specific bits in a register without changing the other bits 4-bit register address Bits with values of 1 in DATA are cleared and bits with values of 0 in register data are not changed.
1111 NOP1 Command for conversion control and reading conversion results N/A N/A
Remaining combinations xxxxxxxxx xxxxxxxxx Reserved These commands are reserved and are treated by the device as no operation
(1) Register data for READ command is provided by device in the next frame.