SBFS042 June   2020 AFE3010

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      GFCI Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Powering The AFE3010
      2. 7.3.2 Sensing Amplifier
      3. 7.3.3 Noise Filter
      4. 7.3.4 ALARM (LED) Driver
      5. 7.3.5 Phase Detection
      6. 7.3.6 SCR Control
      7. 7.3.7 Self-Test Function
        1. 7.3.7.1 Periodic Self-Test
        2. 7.3.7.2 Continuous Self-Test
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pin Configuration
      2. 7.4.2 ALARM Modes to Drive LED
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Manual Self-Test Using PTT Pin
        1. 8.1.1.1 Successful Self-Test
        2. 8.1.1.2 Unsuccessful Self-Test
      2. 8.1.2 ALARM and RESET Function With SW_OPEN
        1. 8.1.2.1 No Self-Test Fail Event
        2. 8.1.2.2 Self-Test Fail Event
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2 Detailed Design Procedure

The following procedure details how to design a GFCI system with the AFE3010. The procedure is not intended to represent all of the validation required for a GFCI system to comply with the necessary regulations. The main goals are to tune the ground fault trip level and neutral-to-ground (N-G) detection of the system.

Table 5 presents the key parameters needed for the components in Figure 15. Table 5 also provides brief explanations of components and parameters. Component voltage ratings are dependent upon either the 20-V internal shunt regulator, the internal 5-V rail, or by the line voltage itself. Note that while Table 5 shows tested and working values, some components could be optimized further to reduce necessary power and voltage ratings depending upon the system requirements.

Table 5. Summary of Components in AFE3010 Typical Application

COMPONENT DESIGNATOR COMPONENT VALUE COMPONENT RATINGS DESCRIPTION
C1 3.3 µF 50 V, ±10%, X7R Primary decoupling capacitance for AFE3010. Voltage rating dependent upon the 20-V shunt regulator.
C2 0.1 µF 50 V, ±10%, NP0 Capacitive load for NG_OUT driver to generate a current pulse. Voltage rating dependent upon the 20-V shunt regulator.
C3 0.47 µF > 5 V, ±10%, X7R Tunes and stabilizes the amplifier response so VOUT is inverted with Line at normal polarity.
C4 1 nF > 5 V, ±10%, NP0 Improves the noise immunity of the amplifier and comparators. TI does not recommend to increase this value further.
C5 1 nF > 5 V, ±10%, NP0 Improves the noise immunity of the amplifier. It can be increased up to 150 nF given R6 and R7 do not change. Always check for amplifier stability over-temperature when increasing this value.
C6 180 pF > 5 V, ±10%, NP0 It helps keep the reference voltage buffer stable from high-frequency noise transients. TI does not recommend to increase this value further.
C7, C8, C9 1 nF > 5 V, ±10%, NP0 These capacitors filter noise coupled to their respective digital pins.
C10 0.47 µF > 5 V, ±10%, X7R These capacitors help prevent noise coupling into the gate of the SCR.
C11 2 .2 nF 250 VAC, ±10%, X7R Helps keep the SCR anode stable. Voltage rating dependent upon line voltage.
D1 N/A 600 V, 1 A Provides line voltage rectification for AFE3010 VDD. Voltage rating dependent upon line voltage.
D2 N/A 1000 V, 1 A Provides current rectification for SCR and solenoid. Voltage rating dependent upon line voltage.
D3 Red Red LED LED driven by ALARM to indicate initial passing of self-test on power up and self-test failure.
D4 N/A 600 V, 1 A Prevents any current flowing from emitter to collector in Q1, which protects the AFE3010 from current injection during abnormal states of Q1.
Q1 400 V 400 V, 1 A NPN transistor controlled by FT driver to perform periodic self-tests.
R1, R2, R3, R4 18.0 kΩ 5%, 0.5 W Limit current for AFE3010 shunt regulator at VDD. Resistors are placed in two parallel pairs to ensure normal operation even if a resistor fails. One pair is placed above the bridge (D1) to limit current in event of a D1 failure. Power rating determined by line voltage and supply current.
R5 100 Ω 1%, 0.1 W Limits current into NG_OUT pin during inductive kickback from driving 200-turn coil. Limiting the current will keep the internal ESD cells from turning on and potentially damaging the device. Thus, take caution when decreasing this value to improve N-G detection. To reduce R5 and protect AFE3010, a Schottky diode can be used at NG_OUT to clamp pin voltage during inductive kickback.
R6 75 Ω 1%, 0.1 W Input resistor for the internal amplifier. R6 can be adjusted to improve N-G detection.
R7 36 kΩ 1%, 0.1 W Feedback resistor for the internal amplifier. Sets the gain for ground fault signals. Thus, R7 can be adjusted to change the device trip point.
R8 10.5 kΩ 1%, 0.5 W Sets the level of fault current used in the periodic self-test when Q1 is turned on. The fault current should be greater than the trip point for successful detection and operation. The self-test will be hardest to pass when line connects to GFCI with reverse polarity and there is a small leakage current that is below the trip current. The worst-case power condition will be when a device cannot detect the self-test fault current and thus Q1 is on for a half-cycle of line.
R9 1.5 kΩ 5%, 0.1 W Limits the output current of the ALARM driver. Using a higher R9 value will reduce supply current when ALARM is driving D3.
R10 560 Ω 5%, 0.1 W Limits the output current of the SCR driver.
R11 51 kΩ 5%, 1/3 W Limits the current into the SCR_TST pin when regulating to 20 V and sets internal biasing. The value of the resistor should not change from the recommendation when SEL = LOW. The lowest acceptable value is a 1% 49.9 kΩ. Given a 170-V peak line voltage, the average power rating required is calculated with [((170 V – 20 V)2) /R11] / [2 × SQRT(2)].
R12 1 MΩ 5%, 0.1 W Limits the current into PH pin.

WARNING

When evaluating this device, implement high-voltage safety precaution and procedures.
  1. The first step in the design of a system with AFE3010 is to determine the correct transformer orientation and coil connections. The AFE3010 internal detection scheme requires the fault waveforms to have a specific polarity to the Hot-to-Neutral line voltage. The two rules the design must follow are:
    1. The amplifier output voltage (VOUT) must be approximately 180° out of phase with the Hot-Neutral line voltage when line voltage connects to a GFCI unit with normal polarity. Thus, when line is connected to system with reverse polarity, the VOUT signal must be in-phase with line voltage. The amplifier's polarity is determined by the value of C3, the connection of amplifier inputs (REF and FB) to the 1000-turn coil, and by the direction of the line wires through the transformer core. Refer to Figure 17 for the correct waveform. Note that normal line polarity means that the Hot and neutral nodes of the source are connected correctly to the Hot and Neutral input connectors of the system, respectively, which means the PH pin and D4 are also connected to Hot as shown in Figure 15.
    2. The N-G pulse on VOUT when there is a N-G fault must look like Figure 18. The N-G pulse measured on VOUT should first increase above 2.5 V and then decrease below 2.5 V. The second, downward pulse should be greater in amplitude and energy than the initial positive pulse. This rule should be true regardless of line polarity. N-G pulse polarity is determined by the connection of NG_OUT and GND pins to the 200-turn coil and by the polarity of the line wires through the transformer core.
  2. Populate the board with the recommended values shown in Table 5.
  3. Tune the amplifier's ground fault threshold (trip point).
    1. Set up the system with an adjustable Hot-to-ground (H-G) fault load and an ammeter in-series to measure the fault (or leakage) current.
    2. Adjust the fault load so that the ammeter reads < 3 mA RMS of fault current.
    3. Power off and then power on the system to reset any possible trips by the system.
    4. Slowly increase the fault current until the AFE3010 SCR driver is pulsed and trips the solenoid. Note the ammeter reading once the system trips.
    5. If the system trips too early (< 4.5 mA RMS), then disconnect the system from power and decrease R7.
    6. If the system trips too late (> 5.5 mA RMS), then disconnect the system from power and increase R7.
  4. Tune the system's Neutral-to-ground (N-G) detection.
    1. Set up the system according to Figure 16. Note that this initial design process does not require testing N-G detection with H-G fault or load currents.
      2. AFE3010 afe3010-neutral-to-ground-detection-test.gifFigure 16. Neutral-to-Ground Detection Test Setup for AFE3010 Design Procedure
    2. Choose the RN and RG pair that creates the largest total resistance, as this is the worst-case for the AFE3010's N-G detection. In this procedure, the total N-G resistance to test is 2 Ω.
    3. Using the relays S1 and S3, switch in the N-G fault and check if the system trips. Note that either relay may be closed first.
    4. If the system successfully trips, then re-test the detection over temperature.
    5. If the system successfully detects N-G fault overtemperature, then the first-pass component optimization is complete.
    6. If the system fails to detect the N-G, then consider the following component modifications:

      1. Adjust R6. Decreasing R6 has shown to increase the N-G pulse sensed by amplifier with minimal effect on amplifier gain.
      2. Increase R7. The trip point must be checked again because the amplifier gain will increase.
      3. Reduce the NG_OUT resistor R5. Note that there is a lower bound to the value of R5, depending on the impedance of the 200-turn coil. R5 helps limit current from any activated internal ESD cells during the inductive kickback on the NG_OUT pin. If R5 must be decreased, consider adding a Schottky diode at the NG_OUT pin to clamp the NG_OUT voltage above the Absolute Maximum Rating of –0.3 V.
      4. Add a small capacitor from the REF pin to GND. Values between 100 pF and 300 pF are acceptable.

  5. Successful operation of the AFE3010 can be seen with the successful passing of the internal self-tests. A successful self-test can be observed with the ALARM LED (D3) blinking once one second after device power up.
  6. Perform the rest of the testing specified in the UL-943 standard.