AFE5816 datasheet

SBAS688E April 2015 – September 2017 AFE5816

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The device supports a wide-frequency bandwidth signal in the range of several kHz to several MHz. The device is a highly-integrated solution that includes an attenuator, low-noise amplifier (LNA), an antialiasing filter, an analog-to-digital converter (ADC), and a continuous-wave (CW) mixer. As a result of the device functionality, the device can be used in various applications (such as in medical ultrasound imaging systems, sonar imaging equipment, radar, and other systems that require a very large dynamic range).

10.2 Typical Application

Figure 102. Simplified Schematic for a Medical Ultrasound Imaging System

Figure 103. Application Circuit

10.2.1 Design Requirements

Typical requirements for a medical ultrasound imaging system are listed in Table 21.

Table 21. Design Parameters

DESIGN PARAMETER	EXAMPLE VALUES
Signal center frequency	5 MHz
Signal bandwidth	2 MHz
Maximum overloaded signal	1 V_PP
Maximum input signal amplitude	100 mV_PP
Transducer noise level	1 nV/√Hz
Dynamic range	151 dBc/Hz
Time-gain compensation range	40 dB
Total harmonic distortion	40 dBc

10.2.2 Detailed Design Procedure

Medical ultrasound imaging is a widely-used diagnostic technique that enables visualization of internal organs, their size, structure, and blood flow estimation. An ultrasound system uses a focal imaging technique that involves time shifting, scaling, and intelligently summing the echo energy using an array of transducers to achieve high imaging performance. The concept of focal imaging provides the ability to focus on a single point in the scan region. By subsequently focusing at different points, an image is assembled.

See Figure 102 for a simplified schematic of a 64-channel ultrasound imaging system. When initiating an ultrasound image, a pulse is generated and transmitted from each of the 64 transducer elements. The pulse, now in the form of mechanical energy, propagates through the body as sound waves, typically in the frequency range of 1 MHz to 15 MHz.

The sound waves weaken rapidly as they travel through the objects being imaged, falling off as the square of the distance traveled. As the signal travels, portions of the wave front energy are reflected. Signals that are reflected immediately after transmission are very strong because they are from reflections close to the surface; reflections that occur long after the transmit pulse are very weak because they are reflecting from deep in the body. As a result of the limitations on the amount of energy that can be put into the imaging object, the industry developed extremely sensitive receive electronics. Receive echoes from focal points close to the surface require little, if any, amplification. This region is referred to as the near field. However, receive echoes from focal points deep in the body are extremely weak and must be amplified by a factor of 100 or more. This region is referred to as the far field. In the high-gain (far field) mode, the limit of performance is the sum of all noise sources in the receive chain.

In high-gain (far field) mode, system performance is defined by its overall noise level, which is limited by the noise level of the transducer assembly and the receive low-noise amplifier (LNA). However, in the low-gain (near field) mode, system performance is defined by the maximum amplitude of the input signal that the system can handle. The ratio between noise levels in high-gain mode and the signal amplitude level in low-gain mode is defined as the dynamic range of the system.

The high integration and high dynamic range of the device make the AFE5816 ideally-suited for ultrasound imaging applications. The device includes an integrated attenuator, an LNA (with variable gain that can be changed with enough time to handle both near- and far-field systems), a low-pass antialiasing filter to limit the noise bandwidth, an ADC with high SNR performance, and a CW mixer. Figure 103 illustrates an application circuit of the device.

The following steps detail how to design medical ultrasound imaging systems:

Use the signal center frequency and signal bandwidth to select an appropriate ADC sampling frequency.
Use the time-gain compensation range to select the range of the LNA gain.
Use the transducer noise level and maximum input signal amplitude to select the appropriate LNA gain. The device input-referred noise level reduces with higher LNA gain. However, higher LNA gain leads to lower input signal swing support.
See Figure 103 to select different passive components for different device pins.
See the CW Clock Selection section to select the clock configuration for the ADC and CW clocks.

10.2.3 Application Curves

Figure 104 and Figure 105 show the FFT of a device output for gain code = 64 and gain code = 319, respectively, with an input signal at 5 MHz captured at a sample rate of 50 MHz. Figure 104 shows the spectrum for a far-field imaging scenario with the full Nyquist band, default device settings, and gain code = 319. Figure 105 shows the spectrum for a near-field imaging scenario for the full Nyquist band with default device settings and gain code = 64.

Figure 104. FFT for Gain Code = 14 dB

Figure 105. FFT for Gain Code = 45 dB

10.3 Do's and Don'ts

Driving the inputs (analog or digital) beyond the power-supply rails. For device reliability, an input must not go more than 300 mV below the ground pins or 300 mV above the supply pins, as suggested in the Absolute Maximum Ratings table. Exceeding these limits, even on a transient basis, can cause faulty or erratic operation and can impair device reliability.

Driving the device signal input with an excessively high-level signal. The device offers consistent and fast overload recovery with a 6-dB overloaded signal. For very large overload signals (> 6 dB of the linear input signal range), TI recommends back-to-back Schottky clamping diodes at the input to limit the amplitude of the input signal.

Not meeting timing requirements on the TGC_SLOPE and TGC_UP_DN pins. If timing is not met between the TGC_SLOPE and TGC_UP_DN signals and the ADC clock signal, then the TGC engine is placed into a locked state. See the Timing Specifications section for more details.

Using a clock source with excessive jitter, an excessively long input clock signal trace, or having other signals coupled to the ADC or CW clock signal trace. These situations cause the sampling interval to vary, causing an excessive output noise and a reduction in SNR performance. For a system with multiple devices, the clock tree scheme must be used to apply an ADC or CW clock. See the System Clock Configuration for Multiple Devices section for clock mismatch between devices, which can lead to latency mismatch and reduction in SNR performance.

LVDS routing length mismatch. The routing length of all LVDS lines routed to the FPGA must be matched to avoid any timing-related issues. For systems with multiple devices, the LVDS serialized data clock (DCLKP, DCLKM) and the frame clock (FCLKP, FCLKM) of each individual device must be used to deserialize the corresponding LDVS serialized data (DOUTP, DOUTM).

Failure to provide adequate heat removal. Use the appropriate thermal parameter listed in the Thermal Information table and an ambient, board, or case temperature in order to calculate device junction temperature. A suitable heat removal technique must be used to keep the device junction temperature below the maximum limit of 105°C.

Incorrect register programming. After resetting the device, write register 1, bit 2 = 1 and register 1, bit 4 = 1. If these bits are not set as specified, the device does not function properly.

10.4 Initialization Set Up

After bringing up all the supplies, follow these steps to initialize the device:

Apply a hardware reset pulse on the RESET pin with a minimum pulse duration of 100 ns. Note that after powering up the device, a hardware reset is required.
After applying a hardware reset pulse, wait for a minimum time of 100 ns.
Set register 1, bit 2 and bit 4 to 1 using SPI signals.
100 µs or later after the start of clock, write the PLLRST1 and PLLRST2 bits to 1. Then, after waiting for at least 10 µs, write both these bits to 0, which helps initialize the PLL in a proper manner. This method of PLL initialization is also required whenever the device comes out of a global power-down mode or when ADC_CLK is switched off and turned on again.
Write any other register settings as required.