SBAS688E April   2015  – September 2017 AFE5816

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Family Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: TGC Mode
    6. 8.6  Electrical Characteristics: CW Mode
    7. 8.7  Digital Characteristics
    8. 8.8  Output Interface Timing Requirements
    9. 8.9  Serial Interface Timing Requirements
    10. 8.10 Typical Characteristics: TGC Mode
    11. 8.11 Typical Characteristics: CW Mode
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Attenuator
        1. 9.3.1.1 Implementation
        2. 9.3.1.2 Maximum Signal Amplitude Support
        3. 9.3.1.3 Attenuator High-Pass Filter (ATTEN HPF)
      2. 9.3.2  Low-Noise Amplifier (LNA)
        1. 9.3.2.1 Input Signal Support in TGC Mode
        2. 9.3.2.2 Input Signal Support in CW Mode
        3. 9.3.2.3 Input Circuit
        4. 9.3.2.4 LNA High-Pass Filter (LNA HPF)
          1. 9.3.2.4.1 Disconnecting the LNA HPF During Overload
        5. 9.3.2.5 LNA Noise Contribution
      3. 9.3.3  High-Pass Filter (HPF)
      4. 9.3.4  Low-Pass Filter (LPF)
      5. 9.3.5  Digital TGC (DTGC)
        1. 9.3.5.1 DTGC Overview
        2. 9.3.5.2 DTGC Programming
          1. 9.3.5.2.1 DTGC Profile
            1. 9.3.5.2.1.1 Profile Selection
        3. 9.3.5.3 DTGC Modes
          1. 9.3.5.3.1 Programmable Fixed-Gain Mode
          2. 9.3.5.3.2 Up, Down Ramp Mode
          3. 9.3.5.3.3 External Non-Uniform Mode
          4. 9.3.5.3.4 Internal Non-Uniform Mode
            1. 9.3.5.3.4.1 Memory
              1. 9.3.5.3.4.1.1 Write Operation for the Memory
              2. 9.3.5.3.4.1.2 Read Operation for the Memory
            2. 9.3.5.3.4.2 Gain Curve Description for the Internal Non-Uniform Mode
        4. 9.3.5.4 Timing Specifications
      6. 9.3.6  Continuous-Wave (CW) Beamformer
        1. 9.3.6.1 16 × ƒcw Mode
        2. 9.3.6.2 8 × ƒcw and 4 × ƒcw Modes
        3. 9.3.6.3 1 × ƒcw Mode
        4. 9.3.6.4 CW Clock Selection
        5. 9.3.6.5 CW Supporting Circuits
      7. 9.3.7  Analog-to-Digital Converter (ADC)
        1. 9.3.7.1 System Clock Input
        2. 9.3.7.2 System Clock Configuration for Multiple Devices
      8. 9.3.8  LVDS Interface
        1. 9.3.8.1 LVDS Buffer
        2. 9.3.8.2 LVDS Data Rate Modes
          1. 9.3.8.2.1 1X Data Rate Mode
          2. 9.3.8.2.2 2X Data Rate Mode
      9. 9.3.9  ADC Register, Digital Processing Description
        1. 9.3.9.1 Digital Offset
          1. 9.3.9.1.1 Manual Offset Correction
          2. 9.3.9.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)
        2. 9.3.9.2 Digital Average
        3. 9.3.9.3 Digital Gain
        4. 9.3.9.4 Digital HPF
        5. 9.3.9.5 LVDS Synchronization Operation
      10. 9.3.10 Power Management
        1. 9.3.10.1 Voltage-Controlled Attenuator (VCA) Power Management
        2. 9.3.10.2 Analog-to-Digital Converter (ADC) Power Management
    4. 9.4 Device Functional Modes
      1. 9.4.1 ADC Test Pattern Mode
        1. 9.4.1.1 Test Patterns
          1. 9.4.1.1.1 LVDS Test Pattern Mode
      2. 9.4.2 Partial Power-Up and Power-Down Mode
      3. 9.4.3 Global Power-Down Mode
      4. 9.4.4 TGC Configuration
      5. 9.4.5 Digital TGC Test Modes
        1. 9.4.5.1 ENABLE_INT_START and NEXT_CYCLE_WAIT_TIME
        2. 9.4.5.2 MANUAL_START
        3. 9.4.5.3 FLIP_ATTEN
        4. 9.4.5.4 DIS_ATTEN
        5. 9.4.5.5 Fixed Attenuation Mode
      6. 9.4.6 CW Configuration
      7. 9.4.7 TGC + CW Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Peripheral Interface (SPI) Operation
        1. 9.5.1.1 Serial Register Write Description
        2. 9.5.1.2 Register Readout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
    4. 10.4 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power Sequencing and Initialization
      1. 11.1.1 Power Sequencing
      2. 11.1.2 PLL Initialization
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Supply, Grounding, and Bypassing
      2. 12.1.2 Board Layout
    2. 12.2 Layout Example
  13. 13Register Maps
    1. 13.1 Serial Register Map
      1. 13.1.1 Global Register Map
        1. 13.1.1.1 Description of Global Register
          1. 13.1.1.1.1 Register 0 (address = 0h)
      2. 13.1.2 ADC Register Map
        1. 13.1.2.1 Description of ADC Registers
          1. 13.1.2.1.1  Register 1 (address = 1h)
          2. 13.1.2.1.2  Register 2 (address = 2h)
          3. 13.1.2.1.3  Register 3 (address = 3h)
          4. 13.1.2.1.4  Register 4 (address = 4h)
          5. 13.1.2.1.5  Register 5 (address = 5h)
          6. 13.1.2.1.6  Register 7 (address = 7h)
          7. 13.1.2.1.7  Register 8 (address = 8h)
          8. 13.1.2.1.8  Register 11 (address = Bh)
          9. 13.1.2.1.9  Register 13 (address = Dh)
          10. 13.1.2.1.10 Register 14 (address = Eh)
          11. 13.1.2.1.11 Register 15 (address = Fh)
          12. 13.1.2.1.12 Register 16 (address = 10h)
          13. 13.1.2.1.13 Register 17 (address = 11h)
          14. 13.1.2.1.14 Register 18 (address = 12h)
          15. 13.1.2.1.15 Register 19 (address = 13h)
          16. 13.1.2.1.16 Register 20 (address = 14h)
          17. 13.1.2.1.17 Register 21 (address = 15h)
          18. 13.1.2.1.18 Register 23 (address = 17h)
          19. 13.1.2.1.19 Register 24 (address = 18h)
          20. 13.1.2.1.20 Register 25 (address = 19h)
          21. 13.1.2.1.21 Register 26 (address = 1Ah)
          22. 13.1.2.1.22 Register 27 (address = 1Bh)
          23. 13.1.2.1.23 Register 28 (address = 1Ch)
          24. 13.1.2.1.24 Register 29 (address = 1Dh)
          25. 13.1.2.1.25 Register 30 (address = 1Eh)
          26. 13.1.2.1.26 Register 31 (address = 1Fh)
          27. 13.1.2.1.27 Register 32 (address = 20h)
          28. 13.1.2.1.28 Register 33 (address = 21h)
          29. 13.1.2.1.29 Register 35 (address = 23h)
          30. 13.1.2.1.30 Register 36 (address = 24h)
          31. 13.1.2.1.31 Register 37 (address = 25h)
          32. 13.1.2.1.32 Register 38 (address = 26h)
          33. 13.1.2.1.33 Register 39 (address = 27h)
          34. 13.1.2.1.34 Register 40 (address = 28h)
          35. 13.1.2.1.35 Register 41 (address = 29h)
          36. 13.1.2.1.36 Register 42 (address = 2Ah)
          37. 13.1.2.1.37 Register 43 (address = 2Bh)
          38. 13.1.2.1.38 Register 44 (address = 2Ch)
          39. 13.1.2.1.39 Register 45 (address = 2Dh)
          40. 13.1.2.1.40 Register 47 (address = 2Fh)
          41. 13.1.2.1.41 Register 48 (address = 30h)
          42. 13.1.2.1.42 Register 49 (address = 31h)
          43. 13.1.2.1.43 Register 50 (address = 32h)
          44. 13.1.2.1.44 Register 51 (address = 33h)
          45. 13.1.2.1.45 Register 52 (address = 34h)
          46. 13.1.2.1.46 Register 53 (address = 35h)
          47. 13.1.2.1.47 Register 54 (address = 36h)
          48. 13.1.2.1.48 Register 55 (address = 37h)
          49. 13.1.2.1.49 Register 56 (address = 38h)
          50. 13.1.2.1.50 Register 57 (address = 39h)
          51. 13.1.2.1.51 Register 59 (address = 3Bh)
          52. 13.1.2.1.52 Register 60 (address = 3Ch)
          53. 13.1.2.1.53 Register 65 (address = 41h)
          54. 13.1.2.1.54 Register 66 (address = 42h)
          55. 13.1.2.1.55 Register 67 (address = 43h)
      3. 13.1.3 VCA Register Map
        1. 13.1.3.1 Description of VCA Registers
          1. 13.1.3.1.1  Register 192 (address = C0h)
          2. 13.1.3.1.2  Register 193 (address = C1h)
          3. 13.1.3.1.3  Register 194 (address = C2h)
          4. 13.1.3.1.4  Register 195 (address = C3h)
          5. 13.1.3.1.5  Register 196 (address = C4h)
          6. 13.1.3.1.6  Register 197 (address = C5h)
          7. 13.1.3.1.7  Register 198 (address = C6h)
          8. 13.1.3.1.8  Register 199 (address = C7h)
          9. 13.1.3.1.9  Register 200 (address = C8h)
          10. 13.1.3.1.10 Register 206 (address = CEh)
          11. 13.1.3.1.11 Register 230 (address = E6h)
      4. 13.1.4 DTGC Register Map
        1. 13.1.4.1 Description of DTGC Register
          1. 13.1.4.1.1 DTGC Registers
            1. 13.1.4.1.1.1  Register 1 (address = 1h)
            2. 13.1.4.1.1.2  Registers 2-160 (address = 2h-A0h)
            3. 13.1.4.1.1.3  Register 161 (address = A1h)
            4. 13.1.4.1.1.4  Register 162 (address = A2h)
            5. 13.1.4.1.1.5  Register 163 (address = A3h)
            6. 13.1.4.1.1.6  Register 164 (address = A4h)
            7. 13.1.4.1.1.7  Register 165 (address = A5h)
            8. 13.1.4.1.1.8  Register 166 (address = A6h)
            9. 13.1.4.1.1.9  Register 167 (address = A7h)
            10. 13.1.4.1.1.10 Register 168 (address = A8h)
            11. 13.1.4.1.1.11 Register 169 (address = A9h)
            12. 13.1.4.1.1.12 Register 170 (address = AAh)
            13. 13.1.4.1.1.13 Register 171 (address = ABh)
            14. 13.1.4.1.1.14 Register 172 (address = ACh)
            15. 13.1.4.1.1.15 Register 173 (address = ADh)
            16. 13.1.4.1.1.16 Register 174 (address = AEh)
            17. 13.1.4.1.1.17 Register 175 (address = AFh)
            18. 13.1.4.1.1.18 Register 176 (address = B0h)
            19. 13.1.4.1.1.19 Register 177 (address = B1h)
            20. 13.1.4.1.1.20 Register 178 (address = B2h)
            21. 13.1.4.1.1.21 Register 179 (address = B3h)
            22. 13.1.4.1.1.22 Register 180 (address = B4h)
            23. 13.1.4.1.1.23 Register 181 (address = B5h)
            24. 13.1.4.1.1.24 Register 182 (address = B6h)
            25. 13.1.4.1.1.25 Register 183 (address = B7h)
            26. 13.1.4.1.1.26 Register 185 (address = B9h)
            27. 13.1.4.1.1.27 Register 186 (address = BAh)
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The device supports a wide-frequency bandwidth signal in the range of several kHz to several MHz. The device is a highly-integrated solution that includes an attenuator, low-noise amplifier (LNA), an antialiasing filter, an analog-to-digital converter (ADC), and a continuous-wave (CW) mixer. As a result of the device functionality, the device can be used in various applications (such as in medical ultrasound imaging systems, sonar imaging equipment, radar, and other systems that require a very large dynamic range).

Typical Application

AFE5816 smplfd_applctn_schm_sbas641.gif Figure 102. Simplified Schematic for a Medical Ultrasound Imaging System
AFE5816 applctn_dgm_sbas641.gif Figure 103. Application Circuit

Design Requirements

Typical requirements for a medical ultrasound imaging system are listed in Table 21.

Table 21. Design Parameters

DESIGN PARAMETER EXAMPLE VALUES
Signal center frequency 5 MHz
Signal bandwidth 2 MHz
Maximum overloaded signal 1 VPP
Maximum input signal amplitude 100 mVPP
Transducer noise level 1 nV/√Hz
Dynamic range 151 dBc/Hz
Time-gain compensation range 40 dB
Total harmonic distortion 40 dBc

Detailed Design Procedure

Medical ultrasound imaging is a widely-used diagnostic technique that enables visualization of internal organs, their size, structure, and blood flow estimation. An ultrasound system uses a focal imaging technique that involves time shifting, scaling, and intelligently summing the echo energy using an array of transducers to achieve high imaging performance. The concept of focal imaging provides the ability to focus on a single point in the scan region. By subsequently focusing at different points, an image is assembled.

See Figure 102 for a simplified schematic of a 64-channel ultrasound imaging system. When initiating an ultrasound image, a pulse is generated and transmitted from each of the 64 transducer elements. The pulse, now in the form of mechanical energy, propagates through the body as sound waves, typically in the frequency range of 1 MHz to 15 MHz.

The sound waves weaken rapidly as they travel through the objects being imaged, falling off as the square of the distance traveled. As the signal travels, portions of the wave front energy are reflected. Signals that are reflected immediately after transmission are very strong because they are from reflections close to the surface; reflections that occur long after the transmit pulse are very weak because they are reflecting from deep in the body. As a result of the limitations on the amount of energy that can be put into the imaging object, the industry developed extremely sensitive receive electronics. Receive echoes from focal points close to the surface require little, if any, amplification. This region is referred to as the near field. However, receive echoes from focal points deep in the body are extremely weak and must be amplified by a factor of 100 or more. This region is referred to as the far field. In the high-gain (far field) mode, the limit of performance is the sum of all noise sources in the receive chain.

In high-gain (far field) mode, system performance is defined by its overall noise level, which is limited by the noise level of the transducer assembly and the receive low-noise amplifier (LNA). However, in the low-gain (near field) mode, system performance is defined by the maximum amplitude of the input signal that the system can handle. The ratio between noise levels in high-gain mode and the signal amplitude level in low-gain mode is defined as the dynamic range of the system.

The high integration and high dynamic range of the device make the AFE5816 ideally-suited for ultrasound imaging applications. The device includes an integrated attenuator, an LNA (with variable gain that can be changed with enough time to handle both near- and far-field systems), a low-pass antialiasing filter to limit the noise bandwidth, an ADC with high SNR performance, and a CW mixer. Figure 103 illustrates an application circuit of the device.

The following steps detail how to design medical ultrasound imaging systems:

  1. Use the signal center frequency and signal bandwidth to select an appropriate ADC sampling frequency.
  2. Use the time-gain compensation range to select the range of the LNA gain.
  3. Use the transducer noise level and maximum input signal amplitude to select the appropriate LNA gain. The device input-referred noise level reduces with higher LNA gain. However, higher LNA gain leads to lower input signal swing support.
  4. See Figure 103 to select different passive components for different device pins.
  5. See the CW Clock Selection section to select the clock configuration for the ADC and CW clocks.

Application Curves

Figure 104 and Figure 105 show the FFT of a device output for gain code = 64 and gain code = 319, respectively, with an input signal at 5 MHz captured at a sample rate of 50 MHz. Figure 104 shows the spectrum for a far-field imaging scenario with the full Nyquist band, default device settings, and gain code = 319. Figure 105 shows the spectrum for a near-field imaging scenario for the full Nyquist band with default device settings and gain code = 64.

AFE5816 D047_BAS624.gif Figure 104. FFT for Gain Code = 14 dB
AFE5816 D048_BAS624.gif Figure 105. FFT for Gain Code = 45 dB

Do's and Don'ts

Driving the inputs (analog or digital) beyond the power-supply rails. For device reliability, an input must not go more than 300 mV below the ground pins or 300 mV above the supply pins, as suggested in the Absolute Maximum Ratings table. Exceeding these limits, even on a transient basis, can cause faulty or erratic operation and can impair device reliability.

Driving the device signal input with an excessively high-level signal. The device offers consistent and fast overload recovery with a 6-dB overloaded signal. For very large overload signals (> 6 dB of the linear input signal range), TI recommends back-to-back Schottky clamping diodes at the input to limit the amplitude of the input signal.

Not meeting timing requirements on the TGC_SLOPE and TGC_UP_DN pins. If timing is not met between the TGC_SLOPE and TGC_UP_DN signals and the ADC clock signal, then the TGC engine is placed into a locked state. See the Timing Specifications section for more details.

Using a clock source with excessive jitter, an excessively long input clock signal trace, or having other signals coupled to the ADC or CW clock signal trace. These situations cause the sampling interval to vary, causing an excessive output noise and a reduction in SNR performance. For a system with multiple devices, the clock tree scheme must be used to apply an ADC or CW clock. See the System Clock Configuration for Multiple Devices section for clock mismatch between devices, which can lead to latency mismatch and reduction in SNR performance.

LVDS routing length mismatch. The routing length of all LVDS lines routed to the FPGA must be matched to avoid any timing-related issues. For systems with multiple devices, the LVDS serialized data clock (DCLKP, DCLKM) and the frame clock (FCLKP, FCLKM) of each individual device must be used to deserialize the corresponding LDVS serialized data (DOUTP, DOUTM).

Failure to provide adequate heat removal. Use the appropriate thermal parameter listed in the Thermal Information table and an ambient, board, or case temperature in order to calculate device junction temperature. A suitable heat removal technique must be used to keep the device junction temperature below the maximum limit of 105°C.

Incorrect register programming. After resetting the device, write register 1, bit 2 = 1 and register 1, bit 4 = 1. If these bits are not set as specified, the device does not function properly.

Initialization Set Up

After bringing up all the supplies, follow these steps to initialize the device:

  1. Apply a hardware reset pulse on the RESET pin with a minimum pulse duration of 100 ns. Note that after powering up the device, a hardware reset is required.
  2. After applying a hardware reset pulse, wait for a minimum time of 100 ns.
  3. Set register 1, bit 2 and bit 4 to 1 using SPI signals.
  4. 100 µs or later after the start of clock, write the PLLRST1 and PLLRST2 bits to 1. Then, after waiting for at least 10 µs, write both these bits to 0, which helps initialize the PLL in a proper manner. This method of PLL initialization is also required whenever the device comes out of a global power-down mode or when ADC_CLK is switched off and turned on again.
  5. Write any other register settings as required.