SBAS688E April   2015  – September 2017 AFE5816

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Family Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: TGC Mode
    6. 8.6  Electrical Characteristics: CW Mode
    7. 8.7  Digital Characteristics
    8. 8.8  Output Interface Timing Requirements
    9. 8.9  Serial Interface Timing Requirements
    10. 8.10 Typical Characteristics: TGC Mode
    11. 8.11 Typical Characteristics: CW Mode
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Attenuator
        1. 9.3.1.1 Implementation
        2. 9.3.1.2 Maximum Signal Amplitude Support
        3. 9.3.1.3 Attenuator High-Pass Filter (ATTEN HPF)
      2. 9.3.2  Low-Noise Amplifier (LNA)
        1. 9.3.2.1 Input Signal Support in TGC Mode
        2. 9.3.2.2 Input Signal Support in CW Mode
        3. 9.3.2.3 Input Circuit
        4. 9.3.2.4 LNA High-Pass Filter (LNA HPF)
          1. 9.3.2.4.1 Disconnecting the LNA HPF During Overload
        5. 9.3.2.5 LNA Noise Contribution
      3. 9.3.3  High-Pass Filter (HPF)
      4. 9.3.4  Low-Pass Filter (LPF)
      5. 9.3.5  Digital TGC (DTGC)
        1. 9.3.5.1 DTGC Overview
        2. 9.3.5.2 DTGC Programming
          1. 9.3.5.2.1 DTGC Profile
            1. 9.3.5.2.1.1 Profile Selection
        3. 9.3.5.3 DTGC Modes
          1. 9.3.5.3.1 Programmable Fixed-Gain Mode
          2. 9.3.5.3.2 Up, Down Ramp Mode
          3. 9.3.5.3.3 External Non-Uniform Mode
          4. 9.3.5.3.4 Internal Non-Uniform Mode
            1. 9.3.5.3.4.1 Memory
              1. 9.3.5.3.4.1.1 Write Operation for the Memory
              2. 9.3.5.3.4.1.2 Read Operation for the Memory
            2. 9.3.5.3.4.2 Gain Curve Description for the Internal Non-Uniform Mode
        4. 9.3.5.4 Timing Specifications
      6. 9.3.6  Continuous-Wave (CW) Beamformer
        1. 9.3.6.1 16 × ƒcw Mode
        2. 9.3.6.2 8 × ƒcw and 4 × ƒcw Modes
        3. 9.3.6.3 1 × ƒcw Mode
        4. 9.3.6.4 CW Clock Selection
        5. 9.3.6.5 CW Supporting Circuits
      7. 9.3.7  Analog-to-Digital Converter (ADC)
        1. 9.3.7.1 System Clock Input
        2. 9.3.7.2 System Clock Configuration for Multiple Devices
      8. 9.3.8  LVDS Interface
        1. 9.3.8.1 LVDS Buffer
        2. 9.3.8.2 LVDS Data Rate Modes
          1. 9.3.8.2.1 1X Data Rate Mode
          2. 9.3.8.2.2 2X Data Rate Mode
      9. 9.3.9  ADC Register, Digital Processing Description
        1. 9.3.9.1 Digital Offset
          1. 9.3.9.1.1 Manual Offset Correction
          2. 9.3.9.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)
        2. 9.3.9.2 Digital Average
        3. 9.3.9.3 Digital Gain
        4. 9.3.9.4 Digital HPF
        5. 9.3.9.5 LVDS Synchronization Operation
      10. 9.3.10 Power Management
        1. 9.3.10.1 Voltage-Controlled Attenuator (VCA) Power Management
        2. 9.3.10.2 Analog-to-Digital Converter (ADC) Power Management
    4. 9.4 Device Functional Modes
      1. 9.4.1 ADC Test Pattern Mode
        1. 9.4.1.1 Test Patterns
          1. 9.4.1.1.1 LVDS Test Pattern Mode
      2. 9.4.2 Partial Power-Up and Power-Down Mode
      3. 9.4.3 Global Power-Down Mode
      4. 9.4.4 TGC Configuration
      5. 9.4.5 Digital TGC Test Modes
        1. 9.4.5.1 ENABLE_INT_START and NEXT_CYCLE_WAIT_TIME
        2. 9.4.5.2 MANUAL_START
        3. 9.4.5.3 FLIP_ATTEN
        4. 9.4.5.4 DIS_ATTEN
        5. 9.4.5.5 Fixed Attenuation Mode
      6. 9.4.6 CW Configuration
      7. 9.4.7 TGC + CW Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Peripheral Interface (SPI) Operation
        1. 9.5.1.1 Serial Register Write Description
        2. 9.5.1.2 Register Readout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
    4. 10.4 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power Sequencing and Initialization
      1. 11.1.1 Power Sequencing
      2. 11.1.2 PLL Initialization
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Supply, Grounding, and Bypassing
      2. 12.1.2 Board Layout
    2. 12.2 Layout Example
  13. 13Register Maps
    1. 13.1 Serial Register Map
      1. 13.1.1 Global Register Map
        1. 13.1.1.1 Description of Global Register
          1. 13.1.1.1.1 Register 0 (address = 0h)
      2. 13.1.2 ADC Register Map
        1. 13.1.2.1 Description of ADC Registers
          1. 13.1.2.1.1  Register 1 (address = 1h)
          2. 13.1.2.1.2  Register 2 (address = 2h)
          3. 13.1.2.1.3  Register 3 (address = 3h)
          4. 13.1.2.1.4  Register 4 (address = 4h)
          5. 13.1.2.1.5  Register 5 (address = 5h)
          6. 13.1.2.1.6  Register 7 (address = 7h)
          7. 13.1.2.1.7  Register 8 (address = 8h)
          8. 13.1.2.1.8  Register 11 (address = Bh)
          9. 13.1.2.1.9  Register 13 (address = Dh)
          10. 13.1.2.1.10 Register 14 (address = Eh)
          11. 13.1.2.1.11 Register 15 (address = Fh)
          12. 13.1.2.1.12 Register 16 (address = 10h)
          13. 13.1.2.1.13 Register 17 (address = 11h)
          14. 13.1.2.1.14 Register 18 (address = 12h)
          15. 13.1.2.1.15 Register 19 (address = 13h)
          16. 13.1.2.1.16 Register 20 (address = 14h)
          17. 13.1.2.1.17 Register 21 (address = 15h)
          18. 13.1.2.1.18 Register 23 (address = 17h)
          19. 13.1.2.1.19 Register 24 (address = 18h)
          20. 13.1.2.1.20 Register 25 (address = 19h)
          21. 13.1.2.1.21 Register 26 (address = 1Ah)
          22. 13.1.2.1.22 Register 27 (address = 1Bh)
          23. 13.1.2.1.23 Register 28 (address = 1Ch)
          24. 13.1.2.1.24 Register 29 (address = 1Dh)
          25. 13.1.2.1.25 Register 30 (address = 1Eh)
          26. 13.1.2.1.26 Register 31 (address = 1Fh)
          27. 13.1.2.1.27 Register 32 (address = 20h)
          28. 13.1.2.1.28 Register 33 (address = 21h)
          29. 13.1.2.1.29 Register 35 (address = 23h)
          30. 13.1.2.1.30 Register 36 (address = 24h)
          31. 13.1.2.1.31 Register 37 (address = 25h)
          32. 13.1.2.1.32 Register 38 (address = 26h)
          33. 13.1.2.1.33 Register 39 (address = 27h)
          34. 13.1.2.1.34 Register 40 (address = 28h)
          35. 13.1.2.1.35 Register 41 (address = 29h)
          36. 13.1.2.1.36 Register 42 (address = 2Ah)
          37. 13.1.2.1.37 Register 43 (address = 2Bh)
          38. 13.1.2.1.38 Register 44 (address = 2Ch)
          39. 13.1.2.1.39 Register 45 (address = 2Dh)
          40. 13.1.2.1.40 Register 47 (address = 2Fh)
          41. 13.1.2.1.41 Register 48 (address = 30h)
          42. 13.1.2.1.42 Register 49 (address = 31h)
          43. 13.1.2.1.43 Register 50 (address = 32h)
          44. 13.1.2.1.44 Register 51 (address = 33h)
          45. 13.1.2.1.45 Register 52 (address = 34h)
          46. 13.1.2.1.46 Register 53 (address = 35h)
          47. 13.1.2.1.47 Register 54 (address = 36h)
          48. 13.1.2.1.48 Register 55 (address = 37h)
          49. 13.1.2.1.49 Register 56 (address = 38h)
          50. 13.1.2.1.50 Register 57 (address = 39h)
          51. 13.1.2.1.51 Register 59 (address = 3Bh)
          52. 13.1.2.1.52 Register 60 (address = 3Ch)
          53. 13.1.2.1.53 Register 65 (address = 41h)
          54. 13.1.2.1.54 Register 66 (address = 42h)
          55. 13.1.2.1.55 Register 67 (address = 43h)
      3. 13.1.3 VCA Register Map
        1. 13.1.3.1 Description of VCA Registers
          1. 13.1.3.1.1  Register 192 (address = C0h)
          2. 13.1.3.1.2  Register 193 (address = C1h)
          3. 13.1.3.1.3  Register 194 (address = C2h)
          4. 13.1.3.1.4  Register 195 (address = C3h)
          5. 13.1.3.1.5  Register 196 (address = C4h)
          6. 13.1.3.1.6  Register 197 (address = C5h)
          7. 13.1.3.1.7  Register 198 (address = C6h)
          8. 13.1.3.1.8  Register 199 (address = C7h)
          9. 13.1.3.1.9  Register 200 (address = C8h)
          10. 13.1.3.1.10 Register 206 (address = CEh)
          11. 13.1.3.1.11 Register 230 (address = E6h)
      4. 13.1.4 DTGC Register Map
        1. 13.1.4.1 Description of DTGC Register
          1. 13.1.4.1.1 DTGC Registers
            1. 13.1.4.1.1.1  Register 1 (address = 1h)
            2. 13.1.4.1.1.2  Registers 2-160 (address = 2h-A0h)
            3. 13.1.4.1.1.3  Register 161 (address = A1h)
            4. 13.1.4.1.1.4  Register 162 (address = A2h)
            5. 13.1.4.1.1.5  Register 163 (address = A3h)
            6. 13.1.4.1.1.6  Register 164 (address = A4h)
            7. 13.1.4.1.1.7  Register 165 (address = A5h)
            8. 13.1.4.1.1.8  Register 166 (address = A6h)
            9. 13.1.4.1.1.9  Register 167 (address = A7h)
            10. 13.1.4.1.1.10 Register 168 (address = A8h)
            11. 13.1.4.1.1.11 Register 169 (address = A9h)
            12. 13.1.4.1.1.12 Register 170 (address = AAh)
            13. 13.1.4.1.1.13 Register 171 (address = ABh)
            14. 13.1.4.1.1.14 Register 172 (address = ACh)
            15. 13.1.4.1.1.15 Register 173 (address = ADh)
            16. 13.1.4.1.1.16 Register 174 (address = AEh)
            17. 13.1.4.1.1.17 Register 175 (address = AFh)
            18. 13.1.4.1.1.18 Register 176 (address = B0h)
            19. 13.1.4.1.1.19 Register 177 (address = B1h)
            20. 13.1.4.1.1.20 Register 178 (address = B2h)
            21. 13.1.4.1.1.21 Register 179 (address = B3h)
            22. 13.1.4.1.1.22 Register 180 (address = B4h)
            23. 13.1.4.1.1.23 Register 181 (address = B5h)
            24. 13.1.4.1.1.24 Register 182 (address = B6h)
            25. 13.1.4.1.1.25 Register 183 (address = B7h)
            26. 13.1.4.1.1.26 Register 185 (address = B9h)
            27. 13.1.4.1.1.27 Register 186 (address = BAh)
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

Overview

The AFE5816 is a highly-integrated, analog front-end (AFE) solution specifically designed for ultrasound systems where high performance and higher integration are required. The device integrates a complete time-gain compensation (TGC) imaging path and a continuous-wave Doppler (CWD) path. The device also enables users to select from a variety of power and noise combinations to optimize system performance. The device contains 16 dedicated channels, each comprising an attenuator, low-noise amplifier (LNA), low-pass filter (LPF), and either a 14-bit or 12-bit analog-to-digital converter (ADC). At the output of the 16 ADCs is a low-voltage differential signaling (LVDS) serializer to transfer digital data. In addition, the device also contains a continuous wave (CW) mixer. Multiple features in the device are suitable for ultrasound applications (such as programmable termination, individual channel control, fast power-up and power-down response, fast and consistent overload recovery, and integrated digital processing). Therefore, this device brings premium image quality to ultra-portable, handheld systems all the way up to high-end ultrasound systems. In addition, the signal chain of the device can handle signal frequencies as low as 10 kHz and as high as 25 MHz. This broad analog frequency range enables the device to be used in both sonar and medical applications; see the Functional Block Diagram section for a simplified function block diagram.

Functional Block Diagram

AFE5816 fbd_sbas641.gif

Feature Description

The device supports two signal chains: TGC mode and CW mode. Table 2 describes the functionality of various blocks in CW and TGC mode.

Table 2. Various Block Functionality in TGC and CW Mode

BLOCK TGC MODE CW MODE
ENABLED, DISABLED COMMENT ENABLED, DISABLED COMMENT
Attenuator Enabled Attenuator supports attenuation range of 8 dB to 0 dB Disabled In CW mode, the attenuator is disabled automatically
Attenuator high-pass filter Enabled Disabled
Low-noise amplifier (LNA) Enabled LNA supports gain range of 14 dB to 45 dB Enabled LNA supports a fixed gain of 18 dB
LNA high-pass filter Enabled Enabled
Low pass filter (LPF) Enabled Disabled In CW mode, the LPF is disabled automatically
Digital TGC (DTGC) Enabled Disabled In CW mode, the DTGC is disabled automatically
Analog-to-digital converter (ADC) Enabled Enabled In CW mode, the ADC remains active. The ADC can be powered down in CW mode using a power-down pin or power-down register bit.

Attenuator

The first stage of the signal chain is an attenuator followed by a low-noise amplifier (LNA). Fundamentally, an attenuator functions as a time-varying passive termination. In ultrasound imaging systems, near-field reflected signals are of very high amplitude. This high-amplitude signal can be attenuated using an attenuator in order to bring the signal amplitude down to within the LNA input amplitude range. The attenuator supports time-gain compensation [that is, the attenuation level is from –8 dB to 0 dB with time in steps of 0.125 dB (64 steps)]. The attenuation level is controlled by the TGC control engine in the device.

Implementation

The attenuator is implemented as a resistor divider network that uses the principle of voltage division between a source resistance (RS) and attenuator resistance (RATTEN); see Figure 56. At the signal frequency, attenuation provided by this resistor network is given by Equation 1:

Equation 1. AFE5816 attenuation_eq_sbas641.gif
AFE5816 attenuator_bd_bas641.gif Figure 56. Attenuator Block Diagram

In Equation 1, the value of the RATTEN resistor is controlled by the TGC control engine. Further details of the TGC control engine are provided in the Digital TGC (DTGC) section. The correct RATTEN network must be selected for a given RS using the INP_RES_SEL register because attenuation is a function of both source resistance (RS) and attenuator resistance (RATTEN). The range of input resistance RS supported is listed in Table 122.

NOTE

The attenuator block remains active only in TGC mode. The attenuator block is disabled in CW mode.

Maximum Signal Amplitude Support

In TGC mode, the maximum input signal amplitude of the low-noise amplifier is approximately 400 mVPP. In Figure 56, the source is modeled as a voltage source at the INP_SOURCE node in series with its (source) impedance RS. The attenuation is achieved by the voltage division between the series combination of the source impedance RS and the attenuator resistance a RATTEN. Therefore, the maximum signal amplitude supported at the INP_SOURCE node is given by 400 mVPP divided by the attenuation. For a given value of source resistance RS, the attenuator provides the maximum attenuation of 8 dB. Thus, the maximum signal supported at the INP_SOURCE node is 1 VPP.

Attenuator High-Pass Filter (ATTEN HPF)

A high-pass filter can be realized through the attenuator. The frequency response of the high-pass filter is governed by the CINM (internal to the device), CINM_EXT (optional and external to the device), and CINP (external ac-coupling capacitor) capacitors, and the source resistance RS and attenuator resistance RATTEN.

For the input circuit shown in Figure 56, the LNA input is given by Equation 2:

Equation 2. AFE5816 lna_inpt_eq_sbas641.gif

where

  • CINM_T represents the total capacitor (= CINM + CINM_EXT) at the INM node.

Equation 2 describes a high-pass response with a corner frequency given by Equation 3:

Equation 3. [1 / (RS + RATTEN)] × [(CINP + CINM_T) / ( CINP × CINM_T)]

Therefore, when RATTEN changes with the TGC, the HPF cutoff frequency also changes.

Figure 57 shows typical values of RATTEN across attenuation and INP_RES_SEL settings. Figure 58 and Figure 59 show the HPF corner frequency across attenuation and INP_RES_SEL settings for CINP = CINM_T =
10 nF and CINP = CINM_T = 1 µF, respectively. For low-frequency application systems (for example, sonar systems that require a very-low, high-pass filter corner), larger value capacitors of CINP and CINM_EXT can be used in order to reduce the HPF corner frequency.

AFE5816 D049_BAS624.gif
Across INP_RES_SEL register settings
Figure 57. Attenuation Resistance vs Attenuation
AFE5816 D051_BAS624.gif
Across INP_RES_SEL register settings, CINP = CINM_T= 1 µF
Figure 59. HPF Corner vs Attenuation
AFE5816 D050_BAS624.gif
Across INP_RES_SEL register settings, CINP = CINM_T = 10 nF
Figure 58. HPF Corner vs Attenuation

Low-Noise Amplifier (LNA)

In many high-gain systems, a LNA is critical to achieve overall performance. The device uses a proprietary architecture and a metal-oxide-semiconductor field-effect transistor (MOSFET) input transistor to achieve exceptional low-noise performance when operating on a low-quiescent current. The LNA takes a single-ended input signal and converts it to a differential output signal.

Input Signal Support in TGC Mode

In TGC mode, the LNA supports time-gain compensation [that is, the LNA gain can be changed from 14 dB to 45 dB in steps of 0.125 dB (256 steps total) with time]. Similar to the attenuator, the LNA gain is also controlled by the TGC control engine.

In TGC mode, the maximum differential swing supported at the LNA output is 2 VPP. Therefore, the maximum swing supported at the LNA input is given by 2 VPP divided by the LNA gain. For an LNA gain of 14 dB, the maximum swing supported at the LNA input is 400 mVPP.

Input Signal Support in CW Mode

In CW mode, the LNA is automatically configured to a 18-dB, fixed-gain mode. In CW mode, the LNA supports a maximum linear input range of 300 mVPP.

Input Circuit

In both CW and TGC modes, the LNA input pin (INPx) is internally biased at approximately 1 V. AC-couple the input signal to the INPx pin with an adequately-sized capacitor, CINP; a 10-nF capacitor is recommended. For low-frequency applications, a 1-µF capacitor is recommended for both CINP and CINM_EXT. The electrical interface of the input attenuator and the LNA to the external world is shown in Figure 60.

AFE5816 lna_inpt_ckt_sbas641.gif Figure 60. Device Input Circuit

LNA High-Pass Filter (LNA HPF)

The LPF circuit in Figure 60 is a low-pass transfer function between the positive and negative inputs of the LNA. The LPF results in a high-pass transfer function between the LNA input and output and can be used to reject unwanted low-frequency leakage signal from the transducer. The high-pass filter in the LNA is active for both CW and TGC mode. The effective corner frequency of the HPF is determined by the capacitor connected at the INMx pin of the device. Internal to the device, a 10-nF capacitor is connected at the INMx node. A large capacitor (such as 1 μF) can be connected externally at the INMx pin for setting the low corner frequency (< 2 kHz) of the LNA dc offset correction circuit. By default, a capacitor is not required to be connected at the INMx pin. To disable this HPF, set the LNA_HPF_DIS register bit to 1. This bit powers down the unity feedback buffer connected between positive and negative input of the LNA shown in Figure 60. For a given INMx capacitor, the corner frequency of the HPF can be programmed using the LNA_HPF_PROG bit. Table 3 lists the HPF corner frequency as a function of the CINM_EXT capacitor connected at the INMx pin across various LNA_HPF_PROG bit settings.

Table 3. HPF Corner Programming Bits

LNA_HPF_PROG HPF CORNER WITHOUT CONNECTING A CAPACITOR AT THE INMx PIN HPF CORNER WITH A CINM_EXT CAPACITOR CONNECTED AT THE INMx PIN
00 75 kHz 75 kHz × 10 nF / (10 nF + CINM_EXT)
01 150 kHz 150 kHz × 10 nF / (10 nF + CINM_EXT)
10 300 kHz 300 kHz × 10 nF / (10 nF + CINM_EXT)
11 600 kHz 600 kHz × 10 nF / (10 nF + CINM_EXT)

Disconnecting the LNA HPF During Overload

In ultrasound systems, the device detects a large-amplitude, overloaded signal during transmit phase. The AFE used for such systems is expected to quickly switch from a high overloaded state to a normal state.

To implement a very low LNA high-pass filter corner, the device uses a large capacitor at the INMx node. The INMx node voltage changes as a result of the large overload signal, which ultimately leads to a low-frequency settling at the device output. To avoid any significant disturbance on the INMx node voltage change resulting from an overloaded input signal, the LNA HPF circuit can be disconnected from the INPx pin by using a series switch; see Figure 60. This switch is controlled by the TR_EN<x>pins (TR_EN<1>, TR_EN<2>, TR_EN<3>, and TR_EN<4> control channels 1 to 4, 5 to 8, 9 to 13, and 14 to 16, respectively). Figure 61 shows an example of TR_EN<x> control signals. Figure 62, Figure 63, Figure 64, and Figure 65 illustrate a positive overload input signal, negative overload input signal, and the corresponding device output for both without and with TR_EN<x> pin functionality, respectively. The TR_EN<x> pin functionality refers to using a low-going pulse on TR_EN<x> during an overload input signal to disconnect the LNA HPF. This functionality is useful when there is not a low-frequency signal immediately after an overload signal.

AFE5816 tr_enble_sgnl_sbas641.gif Figure 61. TR_EN Control Signal
AFE5816 D052_SBAS641.gif Figure 62. Pulse Inversion Positive Input vs Time
AFE5816 D054_SBAS641.gif Figure 64. Overload Recovery Output vs Time Without TR_EN Functionality
AFE5816 D053_SBAS641.gif Figure 63. Pulse Inversion Negative Input vs Time
AFE5816 D055_BAS624.gif Figure 65. Overload Recovery Output vs Time with TR_EN Functionality

LNA Noise Contribution

The noise specification is critical for the LNA and determines the dynamic range of the entire system. The device LNA achieves low power, an exceptionally low-noise voltage of 0.95 nV/√Hz at 45-dB gain, and a low-current noise of 1.2 pA/√Hz in low-noise mode.

Voltage noise is the dominant source of noise; however, the LNA current noise flowing through the source impedance (RS) generates additional voltage noise. The total LNA noise can be computed with Equation 4.

Equation 4. AFE5816 lna_noise_eq_sbas641.gif

The device achieves a low noise figure (NF) over a wide range of source resistances; see Figure 23.

High-Pass Filter (HPF)

Two high-pass filters (HPFs) exist in the signal chain. The first high-pass filter is the HPF that is part of the input attenuator and the other filter is the HPF in the low-noise amplifier (LNA). In the preceding sections (see the LNA High-Pass Filter (LNA HPF) and Attenuator High-Pass Filter (ATTEN HPF) sections) the HPF corner expression of the attenuator and LNA is explained, assuming only a single HPF is active at a time. If both HPFs are enabled at the same time, the overall HPF corner is approximately given by the maximum of the two corner frequencies. For instance, if the HPF corner of the attenuator is (fATTEN) Hz and the HPF corner of the LNA is (fLNA) Hz, the overall HPF corner is given by the maximum of (fATTEN, fLNA) Hz. In CW mode, the attenuator HPF is disabled and the LNA HPF remains active so the overall HPF corner is given by fLNA.

Low-Pass Filter (LPF)

In TGC mode, the LNA output is fed to a low-pass filter (LPF). The LPF is designed as a differential, active, third-order filter with Butterworth characteristics and a typical 18 dB per octave roll-off. Programmable through the serial interface, the –3-dB corner frequency can be set to different combinations across power modes, as shown in Table 4. The filter bandwidth is set for all channels simultaneously.

Note that in CW mode, the LPF is automatically disabled.

Table 4. LPF Corner Frequency Combinations

POWER MODE LPF CORNER FREQUENCY (MHz)
Low noise 10, 15, 20, 25
Medium power 10, 15, 20, 25
Low power 5, 7.5, 10, 12.5

Digital TGC (DTGC)

This section discusses the operation of the digital TGC control engine. The DTGC is relevant only in TGC mode; see the DTGC Register Map for register settings and descriptions.

DTGC Overview

As described previously, the device consists of a programmable attenuator, a variable-gain LNA, and a TGC control engine that controls the gain of the device, as shown in Figure 66. In combination, these blocks can be used to implement a digital time gain control (DTGC) scheme. The attenuator block attenuation can be changed from 8 dB to 0 dB in 0.125-dB steps (64 steps) and the LNA gain can be changed from 14 dB to 45 dB in
0.125-dB steps (256 steps). Thus, the total channel gain can be varied from 6 dB to 45 dB in 0.125-dB steps (320 steps). These gain settings are controlled as a function of time based on the different profile settings of the TGC control engine. The TGC control engine operates on the same clock as the ADC_CLK.

AFE5816 ai_digital_tgc_bas641.gif Figure 66. Digital TGC

DTGC Programming

Various functions of the digital TGC operation can be programmed using the registers listed in the DTGC Register Map. To program register settings in the DTGC register map, set the DTGC_WR_EN bit to 1.

DTGC Profile

The TGC engine supports four different modes (programmable fixed-gain, up, down ramp, external non-uniform, and internal non-uniform mode) to change the device gain with time. The gain versus time curve for each mode is set using a set of combined parameters referred to as a profile. Four such profiles can be programmed in advance, which enables a given mode to switch between one of four profiles based on either a pin control or based on a single register control. Table 5 shows the profile mapping with register bits.

Table 5. Profile Registers Address

PROFILE REGISTER BITS IN THE DTGC REGISTER MAP
0 Registers 161 (bits 15-0), 162 (bits 15-0), 163 (bits 15-0), 164 (bits 15-0), 165 (bits 15-0), and 185 (bits 15-8)
1 Registers 166 (bits 15-0), 167 (bits 15-0), 168 (bits 15-0), 169 (bits 15-0), 170 (bits 15-0), and 185 (bits 7-0)
2 Registers 171 (bits 15-0), 172 (bits 15-0), 173 (bits 15-0), 174 (bits 15-0), 175 (bits 15-0), and 186 (bits 15-8)
3 Registers 176 (bits 15-0), 177 (bits 15-0), 178 (bits 15-0), 179 (bits 15-0), 180 (bits 15-0), and 186 (bits 7-0)

Profile Selection

When programmed, there are two ways that any one of the four profiles can be selected and switched to program the settings in the TGC mode: either with the device pin or by register settings.

  1. Device pin. To select the profile using pin control, set the PROFILE_EXT_DIS bit to 0. Then, the different combinations of logic level at the TGC_PROF<2> and TGC_PROF<1> pins listed in Table 6 dictate which profile is selected.
  2. Register settings. To select the profile with register settings, set the PROFILE_EXT_DIS bit to 1. Then, the different combinations of the PROFILE_REG_SEL bits listed in Table 6 dictate which profile must be used to program the corresponding TGC mode.
  3. Table 6. Profile Selection Using the Device Pin or the PROFILE_REG_SEL Bits

    PIN CONTROL (PROFILE_EXT_DIS = 0) REGISTER CONTROL (PROFILE_EXT_DIS = 1) SELECTED PROFILE
    TGC_PROF<2> TGC_PROF<1> PROFILE_REG_SEL
    0 0 00 Profile 0
    0 1 01 Profile 1
    1 0 10 Profile 2
    1 1 11 Profile 3

DTGC Modes

The device supports four schemes to change the device gain. These schemes are referred to as the four DTGC modes. The device can be programmed in any of these modes by using the MODE_SEL register bit, as shown in Table 7.

Table 7. DTGC Modes

MODE_SEL REGISTER BITS SETTING DTGC MODE
10 Programmable fixed-gain
01 Up, down ramp
00 External non-uniform
11 Internal non-uniform

Programmable Fixed-Gain Mode

In this mode, the device gain is set directly by writing a gain code in the MANUAL_GAIN_DTGC register. See Figure 2 for a description of device gain versus gain code across power modes. Note that the allowed value of the gain code is from 0 to 319. The gain codes from 0 to 63 control the attenuator and the codes from 64 to 319 control the LNA. If the gain code is programmed outside the 0 to 319 range, then the gain code value automatically becomes 0.

For Low-Noise or Medium-Power mode: Gain = 6 + Gain code × 0.125

For Low-Power mode: Gain = 12 + Gain code × 0.125

Up, Down Ramp Mode

Figure 67 shows the change in device gain with time in the up, down ramp mode. This mode generates an ascending gain ramp followed by a descending gain ramp.

AFE5816 up_dwn_mde_sbas641.gif Figure 67. Up, Down Ramp Mode

The different stages of the up, down ramp mode are:

  1. Start: At device reset or a DTGC mode change (that is, when changing the DTGC mode to any other mode and returning to up, down ramp mode), the device gain is equal to the start gain.
  2. Up gain ramp. The up gain ramp stage starts when the TGC_SLOPE pin voltage level goes high. During the up gain ramp stage, the device gain increases by a positive step at the rate of the positive step frequency.
  3. Stop gain. Any device gain in the up gain ramp stage keeps increasing until a stop gain stage is reached. Any pules given at the TGC_SLOPE or TGC_UP_DN pins during the up gain ramp stage are ignored.
  4. Down gain ramp. The down gain ramp stage starts when the TGC_UP_DN pin voltage level goes high. During the down gain ramp stage, the device gain decreases by a negative step at the rate of the negative step frequency. Any device gain in the down gain ramp stage keeps decreasing until a gain reaches the value specified by start gain. Thereafter, the TGC curve proceeds to the start stage.
  5. Profile. Different parameters (such as start gain, positive step, positive step frequency, and so forth) of different gain stages are programmed with profile registers. A single profile consists of five 16-bit registers and one 8-bit register that can be programmed with the serial interface registers. The functions of these registers in up, down ramp mode are listed in Table 8. Note that changing the profile number updates the parameters only during the start gain stage.
  6. Timing requirement. See the section for timing requirements on the TGC_SLOPE and TGC_UP_DN pins with respect to the ADC clock.

Table 8. Profile Description for Up, Down Ramp Mode

REGISTER CONTROL NAME NOTATION IN
REGISTER
MAP
DESCRIPTION DEFAULT
VALUE
ALLOWED
RANGE
PROFILE 0 PROFILE 1 PROFILE 2 PROFILE 3
161
(bits 15-8)
166
(bits 15-8)
171
(bits 15-8)
176
(bits 15-8)
Start gain START_GAIN_x [15:8] These bits set the gain code for the start gain. For an N value (in decimal), these bits set the start gain stage to
(6 + N × 0.25) dB.(1)
0 0 to 159
161
(bits 7-0)
166
(bits 7-0)
171
(bits 7-0)
176
(bits 7-0)
Stop gain STOP_GAIN_x[7:0] These bits set the gain code for the stop gain. For an N value, these bits set the stop gain stage to
(6 + N × 0.25) dB.(1)
159 0 to 159
162
(bits 15-11)
167
(bits 15-11)
172
(bits 15-11)
177
(bits 15-11)
Positive step POS_STEP_x[7:3] For an N value, these bits set the positive step to (N + 1) × 0.125 dB. 0 0 to 31(2)
162
(bits 10-8)
167
(bits 10-8)
172
(bits 10-8)
177
(bits 10-8)
Positive step frequency POS_STEP_x[2:0] For an N value, gain steps at a periodicity of [fS / 2(7 – N)]. Where fS is the ADC clock frequency.(1) 0 0 to 7
162
(bits 7-3)
167
(bits 7-3)
172
(bits 7-3)
177
(bits 7-3)
Negative step NEG_STEP_x[7:3] For an N value, these bits set the negative step to (N + 1) × 0.125 dB.(1) 31 0 to 31
162
(bits 2-0)
167
(bits 2-0)
172
(bits 2-0)
177
(bits 2-0)
Negative step frequency NEG_STEP_x[2:0] For an N value, gain steps at a periodicity of [fS / 2(7 – N)]. Note that fS is ≥ the ADC clock frequency.(1) 7 0 to 7
163 to 165
(bits 15-0)
168 to 170
(bits 15-0)
173 to 175
(bits 15-0)
178 to 180
(bits 15-0)
N/A
185
(bit 15)
185
(bit 7)
186
(bit 15)
186
(bit 7)
FIX_ATTEN_x 0 = Default
1 = Enable fixed attenuation mode
0 0 to 1
185
(bits 14-8)
185
(bits 6-0)
186
(bits 14-8)
186
(bits 6-0)
ATTENUATION_x When the FIX_ATTEN_EN_x bit is set to 1, the attenuation level of the attenuator block is set by the ATTENUATION_0 bits. A value of N written in the ATTENUATION_x register sets the attenuation level at
–8 + N × 0.125 dB.(1)
0 0 to 64
N refers to the decimal equivalent of the multi-bit word.
Best image quality is achieved with a value of N = 0 (positive step of 0.125 dB). Using a higher positive step can result in glitches at the gain transitions, causing a reduction in image quality.

External Non-Uniform Mode

Figure 68 shows the change in device gain with time in external non-uniform mode. This mode generates an ascending gain ramp followed by a descending gain ramp. This mode can be made to generate a non-uniform gain profile using appropriate controls on the TGC_SLOPE and TGC_UP_DN pins.

AFE5816 extrnl_n_mde_sbas641.gif Figure 68. External Non-Uniform Mode

The different stages of the external non-uniform mode are:

  1. Start: At device reset or a DTGC mode change (that is, when changing the DTGC mode to any other mode and returning to external non-uniform mode), the device gain is equal to the start gain.
  2. Increase or decrease gain. When a positive edge transition is received on the device TGC_SLOPE pin, the device gain increases or decreases by either a positive step or negative step based on the TGC_UP_DN pin voltage level. If the TGC_UP_DN pin is set to a level 0, device gain increases and if the TGC_UP_DN pin is set to 1, device gain decreases. The signal frequency at the TGC_SLOPE pin must be less than or equal to the ADC clock.
  3. Profile. Different parameters (such as start gain, positive step, negative step, and so forth) of different gain stages are programmed with profile registers. A single profile consists of five 16-bit registers and one 8-bit register that can be programmed with the serial programming interface (SPI). The functions of these registers in external non-uniform mode are listed in Table 9. Note that changing the profile number updates the parameters at any stage of the gain curve.
  4. Timing requirement. See the section for timing requirements on the TGC_SLOPE and TGC_UP_DN pins with respect to the ADC clock.

Table 9. Profile Description for External Non-Uniform Mode

REGISTER CONTROL NAME BIT IN
REGISTER
MAP
DESCRIPTION DEFAULT
VALUE
ALLOWED
RANGE
PROFILE 0 PROFILE 1 PROFILE 2 PROFILE 3
161
(bits 15-8)
166
(bits 15-8)
171
(bits 15-8)
176
(bits 15-8)
Start gain START_GAIN_x [15:8] These bits set the gain code for the start gain stage. For an N value (in decimal), these bits set the start gain stage to (6 + N × 0.25) dB.(1) 0 0 to 159
161
(bits 7-0)
166
(bits 7-0)
171
(bits 7-0)
176
(bits 7-0)
Stop gain STOP_GAIN_x These bits set the gain code for the stop gain stage. For an N value, these bits set the stop gain stage to
(6 + N × 0.25) dB.(1)
159 0 to 159
162
(bits 15-8)
167
(bits 15-8)
172
(bits 15-8)
177
(bits 15-8)
Positive step POS_STEP_x For an N value, these bits set the positive step to (N + 1) × 0.125 dB.(1) 0 0 to 255(2)
162
(bits 7-0)
167
(bits 7-0)
172
(bits 7-0)
177
(bits 7-0)
Negative step NEG_STEP_x For an N value, these bits set the negative step to (N + 1) × 0.125 dB.(1) 255 0 to 255
163 to 165
(bits 15-0)
168 to 170
(bits 15-0)
173 to 175
(bits 15-0)
178 to 180
(bits 15-0)
185
(bit 15)
185
(bit 7)
186
(bit 15)
186
(bit 7)
FIX_ATTEN_x 0 = Default
1 = Enable fixed attenuation mode
0 0 to 1
185
(bits 14-8)
185
(bits 6-0)
186
(bits 14-8)
186
(bits 6-0)
ATTENUATION_x When the FIX_ATTEN_EN_x bit is set to 1, the attenuation level of the attenuator block is set by the ATTENUATION_0 bits. A value of N written in the ATTENUATION_x register sets the attenuation level at –8 + N × 0.125 dB.(1) 0 0 to 64
N refers to the decimal equivalent of the multi-bit word.
Best image quality is achieved with a value of N = 0 (positive step of 0.125 dB). Using a higher positive step can result in glitches at the gain transitions, causing a reduction in image quality.

Internal Non-Uniform Mode

Figure 69 shows the change in device gain with time in internal non-uniform mode. A gain profile is completely user defined by programming a set of profile registers and a bank of memory consisting of 160 16-bit registers. Programming the profile register is covered in the DTGC Profile section. Memory architecture and other information are explained in detail in the Memory section.

AFE5816 intrnl_n_unfrm_mde_sbas641.gif Figure 69. Internal Non-Uniform Mode

Memory

In the device are a total of four memory banks (bank 0 to bank 3), with each bank containing 160 rows and each row is 16 bits in length, as shown in Figure 70. Each memory bank contains the information of the non-uniform gain curve for a particular profile.

AFE5816 ai_memory_bank_bas641.gif Figure 70. Memory Bank

Write Operation for the Memory

The device supports two write operation modes: normal write mode and burst write mode. The following steps describe the memory write operation in normal write mode:

  1. Select the memory bank whose contents must be programmed using the MEM_BANK_SEL register bit. Table 10 shows the mapping of the MEM_BANK_SEL and memory bank.
  2. Table 10. Memory Bank Selection

    MEM_BANK_SEL MEMORY BANK
    00 0
    01 1
    10 2
    11 3
  3. After selecting the memory bank, any memory bank word can be programmed by writing the MEM_WORD_0 to MEM_WORD_159 registers. For example, to program word 1 to word 160 of memory bank 0, first write MEM_BANK_SEL = 00 and write the memory content at the MEM_WORD_0 to MEM_WORD_159 registers.

The following steps describe the memory write operation in burst write mode:

  1. Select the memory bank whose contents must be programmed using the MEM_BANK_SEL register bit. Table 10 shows the mapping of the MEM_BANK_SEL and memory bank.
  2. After selecting the memory bank, any memory bank word can be programmed in burst by giving the register address only one time. After giving the register address, provide continuous data on the SDIN pin and keep the SEN signal low. The device automatically internally increments the register address and writes the data to the next memory word.

Figure 71 shows the normal and burst write mode operations.

AFE5816 ai_burst_wr_op_bas641.gif Figure 71. Memory Write Mode

Read Operation for the Memory

The memory bank content can be read back in the same manner by reading the registers of the DTGC register map; see the Register Readout section. To read the content of memory banks 0, 1, 2, or 3, first set the MEM_BANK_SEL to 00, 01, 10, or 11 respectively, then place the device in DTGC register read mode and read the MEM_WORD_x register to read word x on the SDOUT pin.

NOTE

Simultaneous memory read and write operation is not supported.

Gain Curve Description for the Internal Non-Uniform Mode

The internal non-uniform mode operation is described in Figure 72 via a flow chart.

AFE5816 flow_chart_tgc_mode_sbas641.gif Figure 72. Internal Non-Uniform Mode Operation

The different stages of the internal non-uniform mode are:

  1. Start: At device reset or a DTGC mode change (that is, when changing the DTGC mode to any other mode and returning to internal non-uniform mode), the device gain is equal to the start gain.
  2. Wait to start: When the TGC_SLOPE pin voltage level goes high, the device gain remains at the start gain stage for the number of ADC clock cycles defined in the START_GAIN_TIME_x register (x is the profile number).
  3. Ramp:
    1. After waiting for START_GAIN_TIME_x number of ADC clock cycles, the TGC engine reads a 16-bit memory word (word[15:0]) at the START_INDEX_x address and performs the following operation:
      1. If memory word[7] = 0, the device gain increases by a positive step gain after waiting for the word[6:0] × 2SLOPE_FAC<3:0>number of ADC clock cycles. If memory word[7] = 1, the device gain decreases by a negative step gain after waiting for the word[6:0] × 2 SLOPE_FAC<3:0>number of ADC clock cycles.
      2. If memory word[15] = 0, the device gain increases by a positive step gain after waiting for the word[14:8] × 2SLOPE_FAC<3:0>number of ADC clock cycles. If memory word[15] = 1, the device gain decreases by a negative step gain after waiting for the word[14:8] × 2SLOPE_FAC<3:0>number of ADC clock cycles.
    2. The TGC engine increases the memory address by 1. If the new address is less than STOP_INDEX_x, the TGC engine reads a 16-bit memory word at the new address and repeats steps i and ii.
  4. Wait to stop: The TGC engine increases the memory address by 1. If the new memory address is equal to STOP_INDEX_x, then the device waits for the STOP_GAIN_TIME_x number of ADC clock cycles.
  5. Ramp down: After waiting for the STOP_GAIN_TIME_x number of ADC clock cycles, the device gain starts reducing by a negative step gain on each ADC clock until the gain reaches the start gain stage.
  6. Profile: Different parameters (such as start gain, positive step, positive step frequency, and so forth) of different gain stages are programmed with profile registers. A single profile consists of five 16-bit registers and one 8-bit register that can be programmed with the serial programming interface (SPI). The functions of these registers in internal non-uniform mode are listed in Table 11. Note that changing the profile number updates the parameters only during the start gain stage.
  7. Timing requirement. See the Timing Specifications section for timing requirements on the TGC_SLOPE pin with respect to the ADC clock.

Table 11. Internal Non-Uniform Mode Profile Definition

REGISTER CONTROL NAME BIT IN
REGISTER
MAP
DESCRIPTION DEFAULT
VALUE
ALLOWED
RANGE
PROFILE 0 PROFILE 1 PROFILE 2 PROFILE 3
161
(bits 15-8)
166
(bits 15-8)
171
(bits 15-8)
176
(bits 15-8)
Start gain START_GAIN_x [15:8] These bits set the gain code for the start gain stage. For an N value (in decimal), these bits set the start gain stage to (6 + N × 0.25) dB. 0 0 to 159
161
(bits 7-0)
166
(bits 7-0)
171
(bits 7-0)
176
(bits 7-0)
STOP_GAIN_x[7:0] Always write 159 159 0 to 159
162
(bits 15-8)
167
(bits 15-8)
172
(bits 15-8)
177
(bits 15-8)
Positive step POS_STEP_x[7:0] For an N value, these bits set the positive step to (N + 1) × 0.125 dB. 0 0 to 255(1)
162
(bits 7-0)
167
(bits 7-0)
172
(bits 7-0)
177
(bits 7-0)
Negative step NEG_STEP_x[7:0] For an N value, these bits set the negative step to (N + 1) × 0.125 dB. 255 0 to 255
163
(bits 15-8)
168
(bits 15-8)
173
(bits 15-8)
178
(bits 15-8)
Memory start index START_INDEX_x Memory start index 0 0 to 159
163
(bits 7-0)
168
(bits 7-0)
173
(bits 7-0)
178
(bits 7-0)
Memory stop index STOP_INDEX_x Memory stop index 159 0 to 159
164
(bits 15-0)
169
(bits 15-0)
174
(bits 15-0)
179
(bits 15-0)
Start gain time START_GAIN_
TIME_x
For an N value, these bits set the start gain time to N × ADC clock cycles. 0 0 to (216 – 1)
165
(bits 15-0)
170
(bits 15-0)
175
(bits 15-0)
180
(bits 15-0)
Stop gain time STOP_GAIN_
TIME_x
For an N value, these bits set the stop gain time to N × ADC clock cycles. 0 0 to (216 – 1)
185
(bit 15)
185
(bit 7)
186
(bit 15)
186
(bit 7)
FIX_ATTEN_x 0 = Default
1 = Enable fixed attenuation mode
0 0 to 1
185
(bits 14-8)
185
(bits 6-0)
186
(bits 14-8)
186
(bits 6-0)
ATTENUATION_x When the FIX_ATTEN_EN_x bit is set to 1, the attenuation level of the attenuator block is set by the ATTENUATION_0 bits. A value of N written in the ATTENUATION_x register sets the attenuation level at –8 + N × 0.125 dB. 0 0 to 64
Best image quality is achieved with a value of N = 0 (positive step of 0.125 dB). Using a higher positive step can result in glitches at the gain transitions, causing a reduction in image quality.

Timing Specifications

For all DTGC modes, a signal applied on the TGC_SLOPE and TGC_UP_DN pins must meet the timing constraints with respect to the ADC clock signal, as shown in Figure 73.

NOTE

Failure to meet the timing constraints in the up, down ramp mode results in a locked state. To come out of a locked start state, change MODE_SEL to another mode and return to up, down ramp mode or reset the device.

AFE5816 ai_tim_tgc_bas641.gif Figure 73. TGC Timing Diagram

A transition on TGC_SLOPE triggers the associated gain change event with a latency. This latency varies depending on the DTGC modes. Table 12 lists the latency for each mode in terms of number of ADC_CLK cycles. To determine the total latency from a transition on TGC_SLOPE to a transition in the output code, the latency of the ADC must be added to the number in Table 12.

Table 12. Latency Between a Transition in TGC_SLOPE and the Resulting Change in Gain

DTGC MODE LATENCY FROM TGC_SLOPE TRANSITION TO A CHANGE IN GAIN
Up, down ramp 6 ADC_CLKs
External non-uniform 2 ADC_CLKs
Internal non-uniform 11 ADC_CLKs

No timing constraints are required on signals applied at the TGC_PROF<2> and TGC_PROF<1> pins.

Continuous-Wave (CW) Beamformer

The continuous-wave Doppler (CWD) is a key function in mid-end to high-end ultrasound systems. Compared to the TGC mode, the CW path must handle high dynamic range along with strict phase noise performance. CW beamforming is often implemented in the analog domain because of these strict requirements. Multiple beamforming methods are implemented in ultrasound systems, including a passive delay line, active mixer, and passive mixer. Among these approaches, the passive mixer achieves optimized power and noise. This mixer satisfies the CW processing requirements (such as wide dynamic range, low phase noise, and accurate gain and phase matching).

The output signal in the CW path is a current output unlike the TGC path that has a voltage output. The down-converted and phase-shifted currents of all the channels are summed and given to a single node; see Figure 74. Connect this node to the virtual ground of an external differential amplifier for correct operation; see Figure 75.

NOTE

The local oscillator inputs of the passive mixer are cos (ωt) for the I channel and sin (ωt) (where ω is local oscillator frequency) for the Q channel, respectively. Depending on the application-specific CWD complex FFT processing, swapping the I and Q channels in either the field-programmable gate array (FPGA) or digital signal processor (DSP) can be required in order to obtain correct blood flow direction.

All blocks include well-matched, in-phase, quadrature channels to achieve good image frequency rejection as well as beamforming accuracy. As a result, the image rejection ratio from an I/Q channel is excellent, which is desired in ultrasound systems.

NOTE

The TGC path in the device is automatically disabled when the CW path is enabled. The device does not support both TGC and CW modes simultaneously. However though not used, the ADC remains powered up by default in the CW mode. The ADC can be powered down using register bit GLOBAL_PDN.

AFE5816 Smplfd_Blck_Dgrm_CW_Pth_bas624.gif Figure 74. Simplified Block Diagram of the CW Path
AFE5816 cw_mode_cmplt_inphs_qdrtr_phs_bas641.gif
NOTE: The 3-Ω to 6-Ω resistors at CW_OUTP and CW_OUTM result from the internal device routing and can create a slight attenuation in the signal.
Figure 75. A Circuit Representation of a In-Phase or Quadrature-Phase Channel

The CW mixing operation attempts to down-convert the signal band to approximately dc such that the Doppler frequency is translated to a low-frequency signal. This process is done by a complex mixing of the signal with a clock that is at the same frequency as the center frequency of the signal. The complex mixing of the signal requires the I- and Q- version of the clock. Furthermore, different channels can have different phase delays in the path of their analog inputs. Thus, the programmability of the phase of the I- and Q- clock is essential to have. The CW mixer uses two clocks; a high speed clock (16X, 8X, or 4X of the mixing clock) that is used to generate multiple phases of a 1X clock, which is at the frequency of the mixing clock.

The CW mixer in the device is passive and switch based; the passive mixer adds less noise than active mixers. The CW mixer achieves good performance at low power. Figure 76, Table 13, and the calculations of Equation 5 describe the principles of the mixer operation. LO(t) is square-wave based and includes odd harmonic components.

AFE5816 mix_bd_LOS688.gif Figure 76. CW Mixer Operation Block Diagram

Table 13. Symbol Definition for CW Mixing

SYMBOL DEFINITION
Vi(t) Input signal to the mixer
Vo(t) Output of the mixer
LO(t) Local oscillator signal (1X clock) with appropriate phase
ω0 Input signal center frequency in radians per second
f0 Input signal center frequency in Hz
ωd Doppler shift frequency in radians per second
t Time
φ Input signal phase relative to the phase of LO(t)
Equation 5. AFE5816 CW_bf_eq_sbas641.gif

All the symbol definitions for Equation 5 are given in Table 13.

The first term in Equation 5 represents the ideal down-connected Doppler frequency component desired from the CW mixer. Though not shown in Equation 5, the third- and fifth-order harmonics from LO(t) can either mix with the third- and fifth-order harmonic of the Vi(t) signal or the noise around the third- and fifth-order harmonics of Vi(t). This higher-order mixing can result in additional undesired down-converted components that lead to degraded mixer performance. In order to eliminate this side-effect resulting from the square-wave demodulation, a proprietary harmonic-suppression circuit is implemented in the device. The third- and fifth-order harmonic components from the LO can be suppressed by over 12 dB. Thus, the LNA output noise around the third- and fifth-order harmonic bands are not down-converted to base band. Thus, a better noise figure is achieved. The conversion loss of the mixer is approximately –4 dB, (20log10 2 / π).

The mixed current output of the 16 channels must be summed externally; see Figure 75. The external differential amplifier converts the current signal to differential voltage and can also provide a filtering action for the higher frequency components in Equation 5. The common-mode voltage at the CW_OUT nodes is 0.9 V. Setting the output common-mode of the external amplifier to 0.9 V is recommended to avoid common-mode loading. The amplifier must be able to support the maximum output current of the device, which is 80 mAPP. The amplifier noise and matching have a direct impact on the I/Q channel performance and therefore must be selected cautiously. Amplifiers with input-referred voltage noise lower than 2 nV/√Hz can be selected. The OPA1632 and THS4130 for are recommended as external amplifiers, both of which satisfy the above criteria.

The CW I/Q channels are well-matched internally to suppress image frequency components in the Doppler spectrum. Use low-tolerance (0.1%) components and precise operational amplifiers to achieve good matching in the external circuits as well. The circuit illustrated in Figure 75 achieves a first-order filter with a corner frequency of fC, as given by Equation 6:

Equation 6. AFE5816 summing_amp_fc_sbas641.gif

The CW path gain (see Figure 75 ) for an in-band signal (frequency less than fC) at one of the channels is given by the combination of LNA gain, mixer loss, and gain provided by the external amplifier. The LNA gain is 18 dB and the mixer attenuation is 4 dB. The gain of the external amplifier is determined by the ratio of the external resistor (Rext) and the internal resistor (500 Ω). The CW gain is given by Equation 7.

Equation 7. AFE5816 cw_channel_gain_eq_sbas641.gif

The 3-Ω to 5-Ω resistors shown in Figure 75 create a small loss. Multiple clock options are supported in the device CW path. Two CW clock inputs are required: an N × ƒcw clock and a 1 × ƒcw clock, where ƒcw is the CW transmitting frequency and N can be 16, 8, 4, or 1. The most convenient system clock solution can be selected for the device. In the 16 × ƒcw and 8 × ƒcw modes, the third- and fifth-order harmonic suppression feature is supported. Thus, the 16 × ƒcw and 8 × ƒcw modes achieve better performance than the 4 × ƒcw and 1 × ƒcw modes.

16 × ƒcw Mode

The 16 × ƒcw mode achieves the best phase accuracy compared to the other modes. This mode is the default mode for CW operation. In this mode, 16 × ƒcw and 1 × ƒcw clocks are required. 16 × fcw generates the 16 × ƒcw LO signals with 16 accurate phases. Multiple devices can be synchronized by the 1 × ƒcw (that is, LO signals in multiple AFEs can have the same starting phase). The phase noise specification is critical only for the 16X clock. The 1X clock is for synchronization only and does not require low phase noise.

The top-level clock distribution diagram is shown in Figure 77. Each mixer clock is distributed through a 16 × 16 cross-point switch. The inputs of the cross-point switch are 16 different phases of the 1X clock. Synchronizing the 1 × ƒcw and 16 × ƒcw clocks is recommended; see Figure 78.

AFE5816 cw_clck_dstrbn_schme_sbas724.gif Figure 77. CW Clock Distribution Scheme
AFE5816 1x_16x_cw_clk_tmng_sbas641.gif Figure 78. 1X and 16X CW Clock Timing Diagram

The cross-point switch distributes the clocks with an appropriate phase delay to each mixer. The mixer phase delay is used to compensate for the delay in the input signal. For instance, if a received signal Vi(t) is delayed with a time of 1 / (16 × fo) (where fo is the input signal frequency in Hz), apply a delayed LO(t) to the mixer in order to compensate for the 1 / (16 × fo) delay. Thus, a 22.5⁰ delayed clock (that is, 2π / 16) is selected for this channel. The mathematical calculation is expressed in Equation 8. Therefore, after the I/Q mixers, the phase delay in the received signals is compensated. The mixer outputs from all channels are aligned and added linearly to improve the signal-to-noise ratio.

Equation 8. AFE5816 EQ8_updated.gif

Vo(t) represents the demodulated Doppler signal of each channel. When the Doppler signals from N channels are summed, the signal-to-noise ratio improves. ωd is the Doppler frequency, ωo is the local oscillator frequency, and ωn represents the high-frequency components that are filtered out.

8 × ƒcw and 4 × ƒcw Modes

The 8 × ƒcw and 4 × ƒcw modes are alternative modes when a higher frequency clock solution (that is, a 16 × ƒcw clock) is not available in the system. The block diagram of these two modes is shown in Figure 79.

AFE5816 ai_fbd_8fcw_4fcw_mode_sbas641.gif Figure 79. 8 × ƒcw and 4 × ƒcw Block Diagram

Good phase accuracy and matching are also maintained in these modes. The quadrature clock generator is used to create in-phase and quadrature clocks with exactly a 90° phase difference. The difference between the 8 × ƒcw and 4 × ƒcw modes is the accessibility of the third- and fifth-order harmonic suppression filter. In the 8 × ƒcw mode, the suppression filter can be supported. Although the phases of the 1X clock that can be directly ensured in the 8 × ƒcw and 4 × ƒcw modes are fewer than in the 16 × ƒcw mode, the intermediate phases can be generated by appropriate weighting and combination of I- and Q- signals. For example, if a delay of 1 / (16 × fo) or 22.5° is targeted corresponding to LO(t), the weighting coefficients must follow Equation 9 (assuming Iin and Qin are sin (ω0t) and cos (ω0t), respectively).

Equation 9. AFE5816 EQ9_updated.gif

NOTE

The timing requirements for the 4 × ƒcw clock relative to the 1 × fcw clock are illustrated in Figure 80. A similar timing requirement (tset and thold) is also applicable for the 8 × ƒcw clock.

AFE5816 8fcw_4fcw_clk_tmg_sbas641.gif Figure 80. 8 × ƒcw and 4 × ƒcw Timing Diagram

1 × ƒcw Mode

The 1 × ƒcw mode requires in-phase and quadrature clocks with low-phase noise specifications. A block diagram for this mode is shown in Figure 81. Here again, the intermediate phases can be obtained through appropriate weighting and combining of the I- and Q- signals, as described in the 8 × ƒcw and 4 × ƒcw Modes section.

AFE5816 ai_fbd_1fcw_mode_sbas641.gif Figure 81. 1 × ƒcw Mode Block Diagram

CW Clock Selection

For the CW clocks, the device can accept differential LVDS, LVPECL, and other differential clock inputs as well as a single-ended CMOS clock. An internally-generated VCM of 1.5 V is applied to CW clock inputs (that is, CW_CLK_NX and CW_CLK1X). Because this 1.5-V VCM is different from the one used in standard LVDS or LVPECL clocks, ac coupling is required between clock drivers and the device CW clock inputs. When the CMOS clock is used, tie CLKM_1X and CLKM_16X either to ground or leave CLKM_1X floating. Common clock configurations are shown in Figure 82. Appropriate termination is recommended to achieve good signal integrity.

NOTE

The configurations shown in Figure 82 can also be used as a reference for the ADC clock input.

AFE5816 ai_clock_configs_sbas724.gif Figure 82. Clock Configurations

The combination of the clock noise and the CW path noise can degrade CW performance. The internal clocking circuit is designed for achieving excellent phase noise required by CW operation. The phase noise of the mixer clock inputs must be better than the phase noise of the CW path.

In the 16, 8, and 4 × ƒcw operation modes, a low-phase noise clock is required for the 16, 8, and 4 × ƒcw clocks (that is, the CW_CLK_NX ) in order to maintain good CW phase noise performance. The 1 × ƒcw clock is only used to synchronize multiple device chips and is not used for demodulation. Thus, the 1 × ƒcw clock phase noise is not a concern. However, in the 1 × ƒcw operation mode, low-phase noise clocks are required for both the CLKP_16X, CLKM_16X and CLKP_1X, CLKM_1X pins because both pins are used for mixer demodulation. In general, a higher slew rate clock has lower phase noise. Thus, clocks with high amplitude and fast slew rate are preferred in CW operation.

Internal to the device, there is a division of the Nx clock (for example, N = 16, 8, or 4) to generate LO(t). A clock division results in improvement of the phase noise. The phase noise of a divided clock can be improved approximately by a factor of 20logN dB, where N is the dividing factor of 16, 8, or 4. If the target phase noise of the mixer LO clock 1 × fcw is 160 dBc/Hz at a 1-kHz off the carrier, the 16 × fcw clock phase noise must be greater than (160 – 20log16 = 136 dBc/Hz). TI’s jitter cleaners (LMK048x, CDCM7005, and CDCE72010) exceed this requirement and can be selected to work with the device. In the 4X and 1X modes, higher-quality input clocks are expected to achieve the same performance because N is smaller. Thus, the 16X mode is a preferred mode because this mode reduces the phase noise requirement for the system clock design.

Note that in the 16X operation mode, the CW operation range is limited to 8 MHz as a result of the 16X clock. The maximum clock frequency for the 16X clock is 128 MHz. In the 8X, 4X, and 1X modes, higher CW signal frequencies up to 15 MHz can be supported with a degradation in performance. For example, the phase noise is degraded by 9 dB at 15 MHz, compared to 2 MHz.

As the channel number in a system increases, clock distribution becomes more complex. Using one clock driver output is not preferred to drive multiple AFEs because the clock buffer load capacitance increases by a factor of N (N is the number of AFEs in a system). See the System Clock Configuration for Multiple Devices section for further details of the system clock configuration. When clock phase noise is not a concern (for example, the 1 × ƒcw clock in the 16, 8, and 4 × ƒcw operation modes), one clock driver output can excite more than one device. Nevertheless, special considerations must be applied for such a clock distribution network design. Preferably, all clocks are generated from the same clock source in typical ultrasound systems (such as 16 × ƒcw and 1 × ƒcw clocks, audio ADC clocks, RF ADC clocks, pulse repetition frequency signals, frame clocks, and so on). By using the same clock source, interference resulting from clock asynchronization can be minimized.

CW Supporting Circuits

As a general practice in the CW circuit design, in-phase and quadrature channels must be strictly symmetrical by using well-matched layout and high-accuracy components. Additional high-pass wall filters (20 Hz to 500 Hz) and low-pass audio filters (10 kHz to 100 kHz) with multiple poles are usually required in ultrasound systems. Noise under this range is critical because the CW Doppler signal ranges from 20 Hz to 20 kHz. Consequently, low-noise audio operational amplifiers are suitable to build these active filters for CW post-processing (that is, the OPA1632, OPA2211, or THS4131). More filter design techniques can be found at www.ti.com. The TI active filter design tool is the WEBENCH® Filter Designer. The filtered audio CW I/Q signals are sampled by audio ADCs and processed by the DSP or PC. Although the CW signal frequency is from 20 Hz to 20 KHz, higher sampling-rate ADCs are still preferred for further decimation and SNR enhancement. Because of the large dynamic range of CW signals, high-resolution ADCs (≥ 16 bits) are required [such as the ADS8413 (2 MSPS, 16 bits, 92-dBFS SNR) and the ADS8472 (1 MSPS, 16 bits, 95-dBFS SNR)]. ADCs for in-phase and quadrature-phase channels must be strictly matched, not only for amplitude matching but also for phase matching in order to achieve the best I/Q matching. In addition, the in-phase and quadrature ADC channels must be sampled simultaneously.

Analog-to-Digital Converter (ADC)

The device supports a high-performance, 14-bit ADC that achieves 72-dBFS SNR. This ADC ensures excellent SNR at low-chain gain. The ADC can operate at maximum speeds of 65 MSPS and 80 MSPS, providing a 14-bit and a 12-bit output, respectively. The low-voltage differential signaling (LVDS) outputs of the ADC enable a flexible system integration that is desirable for miniaturized systems. In the following sections, a full description of all inputs and outputs of the ADC with different configurations are provided along with suitable examples.

NOTE

The ADC is part of the TGC signal chain. An ADC is not used in CW mode and can be powered down in this mode using the appropriate register controls.

System Clock Input

The 16 channels on the device operate from a single clock input. To ensure that the aperture delay and jitter are the same for all channels, the device uses a clock tree network to generate individual sampling clocks for each channel. The clock lines for all channels are matched from the source point to the sampling circuit for each of the 16 internal ADCs. The delay variation is described by the aperture delay parameter of the Output Interface Timing Characteristics table. Variation over time is described by the aperture jitter parameter of the Output Interface Timing Characteristics table.

This system clock input can be driven differentially (sine wave, LVPECL, or LVDS) or single-ended (LVCMOS). The device clock input has an internal buffer and clock amplifier (as shown in Figure 83) that are enabled or disabled automatically, depending on the type of clock provided (auto-detect feature).

AFE5816 Intrnl_Clck_Bffr.gif Figure 83. Internal Clock Buffer for Differential Clock Mode

If the preferred clocking scheme for the device is single-ended, connect the single-ended clock to ADC_CLKP and connect the ADC_CLKM pin to ground (in other words, short ADC_CLKM directly to AVSS, as shown in Figure 84). In this case, the auto-detect feature shuts down the internal clock buffer and the device automatically goes into a single-ended clock mode. Connect the single-ended clock source directly (without decoupling) to the ADC_CLKP pin. Low-jitter, square signals (LVCMOS levels, 1.8-V amplitude) are recommended to drive the ADC in single-ended clock mode (refer to technical brief SLYT075 for further details).

AFE5816 ai_drv_cir_single_sbas641.gif Figure 84. Single-Ended Clock Driving Circuit

For single-ended sinusoidal clocks, or for differential clocks (such as differential sine wave, LVPECL, LVDS, and so forth), enable the clock amplifier with the connection scheme shown in Figure 85. The 10-nF capacitor used to ac-couple the clock input is as shown in Figure 85.

If a transformer is used with the secondary coil floating (for instance, to convert from single-ended to differential), the transformer can be connected directly to the clock inputs without requiring the 10-nF series capacitors, provided that center tap of the transformer is either floating or ac-grounded.

AFE5816 ai_drv_cir_differential_sbas641.gif Figure 85. Differential Clock Driving Circuit

System Clock Configuration for Multiple Devices

To ensure that the aperture delay and jitter are the same for all channels, the device uses a clock tree network to generate individual sampling clocks for each channel. For all channels, the clock is matched from the source point to the sampling circuit of each of the eight internal devices. The variation on this delay is described in the Aperture Delay parameter of the Output Interface Timing Characteristics table. Variation is described by the aperture jitter parameter of the Output Interface Timing Characteristics table.

Figure 86 shows a clock distribution network.

AFE5816 ai_sys_clk_network_sbas41.gif Figure 86. System Clock Distribution Network

LVDS Interface

The device supports an LVDS output interface in order to transfer device digital data serially to an FPGA. The device has a total of 18 LVDS output lines. One of these pairs is a serial data clock, another pair is a data framing clock, and the remaining 16 pairs are dedicated for data transfer. A graphical representation of the LVDS output is shown in Figure 87.

AFE5816 ai_lvds_output_bas623.gif Figure 87. LVDS Output

LVDS Buffer

The equivalent circuit of each LVDS output buffer is shown in Figure 88. The buffer is designed for a normal output impedance of 100 Ω (ROUT). Terminate the differential outputs at the receiver end by a 100-Ω termination. The buffer output impedance functions like a source-side series termination. By absorbing reflections from the receiver end, the buffer output impedance helps improve signal integrity. Note that this internal termination cannot be disabled nor can its value be changed.

AFE5816 ai_lvds_output_cir_bas623.gif Figure 88. LVDS Output Circuit

LVDS Data Rate Modes

The LVDS interface supports two data rate modes, as described in this section.

1X Data Rate Mode

In 1X data rate mode, each LVDS output carries data from a single ADC. Figure 89 and Figure 90 show the output data, serial clock, and frame clock LVDS lines for the 14-bit and 12-bit 1X mode, respectively.

AFE5816 14b_1x_mode_sbas641.gif
K = ADC resolution.
Figure 89. 14-Bit, 1X Data Rate Output Timing Specification
AFE5816 12b_1x_mode_sbas641.gif Figure 90. 12-Bit, 1X Data Rate Output Timing Specification

2X Data Rate Mode

In 2X data rate mode, only half of the LVDS lines are used to transfer data. Thus, this mode is useful for saving power when lower sampling frequency ranges permit. This mode is enabled with the LVDS_RATE_2X register bit (register 1, bit 14). After enabling this mode, the digital data from two ADCs are transmitted with a single LVDS lane. When compared to the 1X data rate mode, the 2X data rate mode serial clock frequency is doubled, but the frame clock frequency remains the same (for the same serialization factor and ADC resolution).

When the frame clock is high, data on DOUT1 correspond to channel 1, data on DOUT2 correspond to channel 3, and so forth. When the frame clock is low, DOUT1 transmits channel 2 data, DOUT2 transmits channel 4 data, and so forth.

Figure 91 and Figure 92 show a timing diagram for the 14-bit and 12-bit 2X mode, respectively. Channel and LVDS data line mapping for this mode are listed in Table 14. Note that idle LVDS lines are not powered down by default. To save power, these lines can be powered down using the corresponding power-down bits (PDN_LVDSx).

AFE5816 14b_2x_mode_sbas641.gif Figure 91. 14-Bit, 2X Data Rate Output Timing Specification
AFE5816 12b_2x_mode_sbas641.gif Figure 92. 12-Bit, 2X Data Rate Output Timing Specification

Table 14 illustrates which LVDS output lines are active in 2X data rate mode. The idle channels can be powered down using appropriate register controls.

Table 14. Channel and ADC Data Line Mapping (2X Rate)

CHANNELS MAPPING
DOUT1 ADC data for channels 1 and 2
DOUT2 ADC data for channels 3 and 4
DOUT3 ADC data for channels 5 and 6
DOUT4 ADC data for channels 7 and 8
DOUT5 Idle
DOUT6 Idle
DOUT7 Idle
DOUT8 Idle
DOUT9 ADC data for channels 9 and 10
DOUT10 ADC data for channels 11 and 12
DOUT11 ADC data for channels 13 and 14
DOUT12 ADC data for channels 15 and 16
DOUT13 Idle
DOUT14 Idle
DOUT15 Idle
DOUT16 Idle

ADC Register, Digital Processing Description

The ADC has extensive digital processing functionalities that can be used to enhance ADC output performance. The digital processing blocks are arranged as shown in Figure 93.

AFE5816 dig_ADC_BD_BAS623.gif Figure 93. ADC Digital Block Diagram

Digital Offset

Digital functionality provides for channel offset correction. Setting the DIG_OFFSET_EN bit to 1 enables the subtraction of the offset value from the ADC output. There are two offset correction modes, as shown in Figure 94.

AFE5816 dgtl_offset_blk_dgm_sbas641.gif Figure 94. Digital Offset Correction Block Diagram

Manual Offset Correction

If the channel offset is known, the appropriate value can be written in the OFFSET_CHx register for channel x. The offset value programmed in the OFFSET_CHx register subtracts out from the ADC output. The offset of each of the 16 ADC output channels can be independently programmed. The same offset value must be programmed into two adjacent offset registers. For instance, when programming the channel 1 offset value 0000011101, write the same offset value of 0000011101 in registers 13 (bits 9-0) and 14 (bits 9-0). The offset values are to be written in twos complement format.

Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)

The auto offset calculation module can be used to calculate the channel offset that is then subtracted from the ADC output. To enable the auto offset correction mode, set the OFFSET_REMOVAL_SELF bit to 0.

In auto offset correction mode, the dc component of the ADC output (assumed to be the channel offset) is estimated using a digital accumulator. The ADC output sample set used by the accumulator is determined by a start time or by the first sample and number of samples to be used. Figure 94 illustrates the options available to determine the accumulator sample set. A high pulse on the TX_TRIG pin or setting the OFFSET_REMOVAL_START_MANUAL register can be used to determine the accumulator first sample. To set the number of samples, the AUTO_OFFSET_REMOVAL_ACC_CYCLES register (bits 12-9) must be programmed according to Table 15.

If a pulse on the TX_TRIG pin is used to set the first sample, additional flexibility in setting the first sample is provided. A programmable delay between the TX_TRIG pulse and first sample can be set by writing to the OFFSET_CORR_DELAY_FROM_TX_TRIG register.

The determined offset value can be read out channel-wise. Set the channel number in the AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL register and read the offset value for the corresponding channel in the AUTO_OFFSET_REMOVAL_VAL_RD register.

Table 15. Auto Offset Removal Accumulator Cycles

AUTO_OFFSET_REMOVAL_ACC_CYCLES (Bits 3-0) NUMBER OF SAMPLES USED FOR OFFSET VALUE EVALUATION
0 2047
1 127
2 255
3 511
4 1023
5 2047
6 4095
7 8191
8 16383
9 32767
10 to 15 65535

Digital Average

The signal-to-noise ratio (SNR) of the signal chain can be improved by providing the same input signal to two channels and averaging their output digitally. To enable averaging, set the AVG_EN register bit (register 2, bit 11). The way that data are transmitted on the digital output lines in this mode is described in Table 16.

Table 16. Channel and ADC Data Line Mapping (Averaging Enabled)

CHANNELS MAPPING
DOUT1 Average of channels 1 and 2
DOUT2 Average of channels 3 and 4
DOUT3 Average of channels 5 and 6(1)
DOUT4 Average of channels 7 and 8(1)
DOUT5 Idle
DOUT6 Idle
DOUT7 Idle
DOUT8 Idle
DOUT9 Average of channels 9 and 10
DOUT10 Average of channels 11 and 12
DOUT11 Average of channels 13 and 14(1)
DOUT12 Average of channels 15 and 16(1)
DOUT13 Idle
DOUT14 Idle
DOUT15 Idle
DOUT16 Idle
Idle when AVG_EN = 1 and when the LVDS data rate is set to 2X mode.

NOTE

Idle LVDS lines are not powered down by default. To save power, these lines can be powered down using the corresponding power-down bits (PDN_LVDSx).

The serialization factor must be greater than the ADC resolution to obtain SNR improvement after averaging in 12b resolution.

Digital Gain

To enable the digital gain block, set DIG_GAIN_EN (register 3, bit 12) to 1. When enabled, the gain value for channel x (where x is from 1 to 16) can be set with the 4-bit register control for the corresponding channel (GAIN_CHx). Gain is given as (0 dB + 0.2 dB × GAIN CHx). For instance, if GAIN_CH5 = 3 (decimal equivalent of the 4-bit word), then channel 5 is increased by a 0.6-dB gain. GAIN_CHx = 31 produces the same effect as GAIN_CHx = 30, which sets the gain of channel x to 6 dB.

Digital HPF

To enable the digital high-pass filter (HPF) of channels 1 to 4, 5 to 8, 9 to 12, and 13 to 16, set the DIG_HPF_EN_CH1-4, DIG_HPF_EN_CH5-8, DIG_HPF_EN_CH9-12, and DIG_HPF_EN_CH13-16, respectively.

The HPF_CORNER_CHxy register bits (where xy are 1-4, 5-8, 9-12, or 13-16) control the characteristics of a digital high-pass transfer function applied to the output data, based on Equation 10. These bits correspond to bits 4-1 in registers 21, 33, 45, and 57, respectively (these register settings describe the value of K). The valid values of K are 2 to 10. The digital HPF can be used to suppress low-frequency noise. Table 17 describes the cutoff frequency versus K.

Equation 10. AFE5816 q_yn_bas623.gif

Table 17. Digital HPF, –1-dB Corner Frequency versus K and fS

CORNER FREQUENCY (k)
(HPF_CORNER_CHxy Register)
CORNER FREQUENCY (kHz)
fS = 40 MSPS fS = 50 MSPS fS = 65 MSPS
2 2780 3480 4520
3 1490 1860 2420
4 738 230 1200
5 369 461 600
6 185 230 300
7 111 138 180
8 49 61 80
9 25 30 40
10 12. 15 20

The HPF output is mapped to the ADC resolution bits either by truncation or a round-off operation. By default, the HPF output is truncated to map to the ADC resolution. To enable the rounding operation to map the HPF output to the ADC resolution, set the HPF_ROUND_EN_CH1-8 and HPF_ROUND_EN_CH9-16 bits to 1.

LVDS Synchronization Operation

Different test patterns can be synchronized on the LVDS serialized output lines to help set and program the FPGA timing that receives the LVDS serial output. Of these test patterns, the ramp, toggle, and pseudo-random sequence (PRBS) test patterns can be reset or synchronized by providing a synchronization pulse on the TX_TRIG pin or by setting and resetting a specific register bit. The synchronization pulse on the TX_TRIG pin must meet the setup and hold time constraints with respect to the system clock, as shown in Figure 95. Parameter values are listed in the Output Interface Timing Requirements table.

AFE5816 TX_TRIG_32_Inp_sbas641.gif Figure 95. Setup and Hold Time Constraint for the TX_TRIG Signal

ADC data may be corrupted for four to six clocks immediately after applying TX_TRIG. The phase reset from TX_TRIG can be disabled using MASK_TX_TRIG.

Power Management

Power management plays a critical role to extend battery life and to ensure a long operation time. The device has a fast and flexible power-up and power-down control that can maximize battery life. The device can be either powered down or up through external pins or internal registers.

This section describes the functionality of different power-down pins and register bits available in the device. The device can be divided in two major blocks: the VCA and ADC; see Figure 96 and Figure 97.

AFE5816 vca_blck_dgm_sbas641.gif Figure 96. VCA Block Diagram
AFE5816 ADC_block_dia_BAS624.gif Figure 97. ADC Block Diagram

Voltage-Controlled Attenuator (VCA) Power Management

The VCA consists of the following blocks:

  • Band-gap circuit,
  • Serial interface,
  • Reference voltage and current generator,
  • A total of 16 channel blocks (each channel block includes an attenuator, LNA, LPF, CW mixer, and a 16 × 16 cross-point switch),
  • TGC control engine, and
  • Phase generator for CW mode.

Of these VCA blocks, the band-gap, attenuator, and serial interface block cannot be powered down by using power-down pins or bits. Table 18 lists all the VCA blocks that are powered down using various pin and bit settings.

Table 18. VCA Power-Down Mode Descriptions

NAME TYPE
(Pin or Register)
LNA LPF CW MIXER 16 × 16 CROSS-POINT SWITCH TGC CONTROL ENGINE REFERENCE PHASE GENERATOR CHANNEL
PDN_GBL Pin Yes(1) Yes Yes Yes Yes Yes Yes All(2)
GBL_PDWN Register Yes Yes Yes Yes Yes Yes Yes All
PDN_FAST Pin Yes Yes Yes Yes No No Yes All
FAST_PDWN Register Yes Yes Yes Yes No No Yes All
PDCHxx Register Yes Yes Yes Yes No No No Individual
PDWN_LNA Register Yes No No No No No No All
PDWN_
FILTER
Register No Yes No No No No No All
Yes = powered down; no = active.
All = all channels are powered down; individual = only a single channel is powered down, depending upon the corresponding bit.

If more than one bit is simultaneously enabled, then all blocks listed as Yes for each bit setting are powered down.

Analog-to-Digital Converter (ADC) Power Management

The ADC consists of the following blocks:

  • Band-gap circuit,
  • Serial interface,
  • Reference voltage and current generator,
  • ADC analog block that performs a sampling and conversion,
  • ADC digital block that includes all the digital post processing blocks (such as the offset, gain, digital HPF, and so forth),
  • LVDS data serializer and buffer that converts the ADC parallel data to a serial stream,
  • LVDS frame and clock serializer and buffer, and
  • PLL (phase-locked loop) that generates a high-frequency clock for both the ADC and serializer.

Of all these blocks, only the band-gap and serial interface block cannot be powered down using power-down pins or bits. Table 19 lists which blocks in the ADC are powered down using different pins and bits.

Table 19. Power-Down Modes Description for the ADC

NAME TYPE (Pin or Register) ADC ANALOG ADC DIGITAL LVDS DATA SERIALIZER, BUFFER LVDS FRAME AND CLOCK SERIALIZER, BUFFER REFERENCE + ADC CLOCK BUFFER PLL CHANNEL
PDN_GBL Pin Yes(1) Yes Yes Yes Yes Yes All(2)
GLOBAL_PDN Register Yes Yes Yes Yes Yes Yes All
PDN_FAST Pin Yes Yes Yes No No No All
DIS_LVDS Register No No Yes Yes No No All
PDN_ANA_CHx Register Yes No No No No No Individual
PDN_DIG_CHx Register No Yes No No No No Individual
PDN_LVDSx Register No No Yes No No No Individual
Yes = powered down; no = active.
All = all channels are powered down; individual = only a single channel is powered down, depending upon the corresponding bit.

Device Functional Modes

ADC Test Pattern Mode

Test Patterns

LVDS Test Pattern Mode

The ADC data coming out of the LVDS outputs can be replaced by different kinds of test patterns. The different test patterns are described in Table 20.

Table 20. Description of LVDS Test Patterns

TEST PATTERN MODE PROGRAMMING THE MODE TEST PATTERNS REPLACE(1)
THE SAME PATTERN MUST BE COMMON TO ALL DATA LINES (DOUT) THE PATTERN IS SELECTIVELY REQUIRED ON ONE OR MORE DATA LINE (DOUT)
All 0s Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] Zeros in all bits (00000000000000)
All 1s Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] Ones in all bits (11111111111111)
Deskew Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] The ADC data is replaced by alternate 0s and 1s (01010101010101)
Sync Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] ADC data are replaced by half 1s and half 0s (11111110000000)
Custom Set the mode using PAT_MODES[2:0]. Set the desired custom pattern using the CUSTOM_PATTERN register control. Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] The word written in the CUSTOM_PATTERN control (taken from the MSB side) replaces ADC data.
(For instance, CUSTOM_PATTERN = 1100101101011100 and ADC data = 11001011010111 when the serialization factor is 14.)
Ramp Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] The ADC data are replaced by a word that increments by 1 LSB every conversion clock starting at negative full-scale, increments until positive full-scale, and wraps back to negative full-scale. Step size of RAMP pattern is function of ADC resolution (N) and serialization factor (S) and given by 2(S-N).
Toggle Set the mode using PAT_MODES[2:0] Set PAT_SELECT_IND = 1. To output the pattern on the DOUTx line, select PAT_LVDSx[2:0] The ADC data alternate between two words that are all 1s and all 0s. At each setting of the toggle pattern, the start word can either be all 0s or all 1s. (Alternate between 11111111111111 and 00000000000000.)
PRBS Set SEL_PRBS_PAT_GBL = 1. Select either custom or ramp pattern with PAT_MODES[2:0]. Enable PRBS mode using PRBS_EN. Select the desired PRBS mode using PRBS_MODE. Reset the PRBS generator with PRBS_SYNC. Set PAT_SELECT_IND = 1. Select either custom or ramp pattern with PAT_LVDSx[2:0]. Enable PRBS mode on DOUTx with the PAT_PRBS_LVDSx control. Select the desired PRBS mode using PRBS_MODE. Reset the PRBS generator with PRBS_SYNC. A 16-bit pattern is generated by a 23-bit (or 9-bit) PRBS pattern generator (taken from the MSB side) and replaces the ADC data.
Shown for a serialization factor of 14.

All patterns listed in Table 20 (except the PRBS pattern) can also be forced on the frame clock output line by using PAT_MODES_FCLK[2:0]. To force a PRBS pattern on the frame clock, use the SEL_PRBS_PAT_FCLK, PRBS_EN, and PAT_MODES_FCLK register controls.

The ramp, toggle, and pseudo-random sequence (PRBS) test patterns can be reset or synchronized by providing a synchronization pulse on the TX_TRIG pin or by setting and resetting a specific register bit. A block diagram for the test patterns is provided in Figure 98.

AFE5816 ai_fbd_test_pattern_bas623.gif Figure 98. Test Pattern Block Diagram

Partial Power-Up and Power-Down Mode

The partial power-up and power-down mode is also called fast power-up and power-down mode. The VCA can be programmed in partial power-down mode either by setting the PDN_FAST pin high or setting the FAST_PDWN register bit to 1. Similarly, the ADC can be programmed in this mode by setting the PDN_FAST pin high. In this mode, many blocks in the signal path are powered down. However, the internal reference circuits, LVDS frame, and data clock buffers remain active. The partial power-down function allows the device to quickly wake-up from a low-power state. This configuration ensures that the external capacitors are discharged slowly; thus, a minimum wake-up time is required as long as the charges on these capacitors are restored. The longest wake-up time depends on the capacitors connected at INP and INM, because the wake-up time is the time required to recharge the capacitors to the desired operating voltages. For larger capacitors, this time is longer. The ADC wake-up time is approximately 1 μs. Thus, the device wake-up time is more dependent on the VCA wake-up time with the assumption that the ADC clock is running for at least 50 μs before the normal operating mode resumes. The power-down time is instantaneous, less than 2 μs. This fast wake-up response is desired for portable ultrasound applications where power savings is critical. The pulse repetition frequency (PRF) of an ultrasound system can vary from 50 kHz to 500 Hz, and the imaging depth (that is, the active period for a receive path) varies from tens of µs to hundreds of μs. The power savings can be quite significant when a system PRF is low. In some cases, only the VCA is powered down when the ADC runs normally to ensure minimal interference to the FPGAs; see the Electrical Characteristics: TGC Mode table to determine device power dissipation in partial power-down mode.

The AFE uses PLLs that generate the high speed clock for the interfaces. Switching activity on the PDN_FAST pin can possibly result in disturbance to the PLL operation because of board-level coupling mechanisms. Such a disturbance can result in a loss of synchronization at the FPGA and may require re-synchronization on resumption of normal operation.

Global Power-Down Mode

To achieve the lowest power dissipation, the device can be placed into a complete power-down mode. This mode is controlled through the GBL_PDWN (for the VCA) or GLOBAL_PDN (for the ADC) registers or the PDN_GBL pin (for both the VCA and ADC). In complete power-down mode, all circuits (including reference circuits within the device) are powered down and the capacitors connected to the device are discharged. The wake-up time depends on the time that the device spends in shutdown mode. A 0.01-μF capacitor at INP without a capacitor at INM provides a wake-up time of approximately 1 ms.

TGC Configuration

By default, the VCA is configured in TGC mode after reset. Depending upon the system requirements, the device can be programmed in a suitable power mode using the MEDIUM_POW (register 206, bit 14) and LOW_POW (register 200, bit 12) register bits.

Digital TGC Test Modes

The available test mode bits in the TGC engine are: ENABLE_INT_START, NEXT_CYCLE_WAIT_TIME, MANUAL_START, FLIP_ATTEN, and DIS_ATTEN.

ENABLE_INT_START and NEXT_CYCLE_WAIT_TIME

In internal non-uniform digital TGC mode, the device gain starts changing after the TGC_SLOPE pin level goes high. Instead of applying a signal on the TGC_SLOPE pin, the device generates a signal to start the device gain. To generate a signal internally, set the ENABLE_INT_START bit (register 181, bit 14) to 1. When a complete cycle of the gain curve completes and the device gain returns to the start gain stage, the next start pulse is generated after the NEXT_CYCLE_WAIT_TIME (register 183, bits 15-0) number of ADC clock cycles, as shown in Figure 99.

AFE5816 enable_int_start_test_sbas641.gif Figure 99. Internal Non-Uniform Test Mode

MANUAL_START

In up, down ramp mode and internal non-uniform mode, a single TGC start pulse provided on the TGC_SLOPE pin can be generated by the device when the MANUAL_START bit is enabled. In up, down ramp mode, the MANUAL_START bit also generates a pulse that performs the same functionality that applying a pulse on the TGC_UP_DOWN pin does (that is, reduces the signal gain from stop gain to start gain).

FLIP_ATTEN

By default, the attenuation of an attenuator block is varied and followed by an LNA gain variation in all TGC modes. When the FLIP_ATTEN bit (register 182, bit 6) is enabled, the LNA gain is varied first and then followed by the attenuation of an attenuator block.

DIS_ATTEN

When the DIS_ATTEN bit is set to 1, the attenuation block is disabled.

Fixed Attenuation Mode

The attenuator block can be programmed in fixed attenuation mode (that is, the attenuation does not change with time by enabling the FIX_ATTEN_x (x is the profile number) bit in the DTGC Register Map). When the FIX_ATTEN_x bit is set to 1, the attenuation value is set using the ATTENUATION_x register bits. A value of N written in the ATTENUATION_x register sets the attenuation level at –8 + N × 0.125 dB.

CW Configuration

To configure the device in CW mode, set the CW_TGC_SEL register bit (register 192, bit 0) to 1. To save power, the ADC can be powered down completely using the GLOBAL_PDN bit (register 1, bit 0). Usually only half the number of channels in a system are active in the CW mode. Thus, the individual channel control can power-down unused channels and save power; see Table 18 and Table 19. Enabling CW mode automatically configures the LNA from TGC mode to CW mode and disables the LPF stage.

TGC + CW Mode

This device does not support TGC and CW mode simultaneously. Only one mode can remain active at a time.

Programming

Serial Peripheral Interface (SPI) Operation

This section discusses the read and write operations of the SPI interface.

Serial Register Write Description

Several different modes can be programmed with the serial peripheral interface (SPI). This interface is formed by the SEN (serial interface enable), SCLK (serial interface clock), SDIN (serial interface data), and RESET pins. The SCLK, SDIN, and RESET pins have a 16-kΩ pulldown resistor to ground. SEN has a 16-kΩ pullup resistor to supply. Serially shifting bits into the device is enabled when SEN is low. SDIN serial data are latched at every SCLK rising edge when SEN is active (low). SDIN serial data are loaded into the register at every 24th SCLK rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of 24-bit words within a single active SEN pulse (an internal counter counts the number of 24 clock groups after the SEN falling edge). Data are divided into two main portions: the register address (8 bits) and data (16 bits). Figure 100 shows the timing diagram for serial interface write operation.

AFE5816 ai_tim_serial_bas623.gif Figure 100. Serial Interface Timing

Register Readout

The device includes an option where the contents of the internal registers can be read back. This readback can be useful as a diagnostic test to verify the serial interface communication between the external controller and AFE. First, the REG_READ_EN bit must be set to 1. Then, initiate a serial interface cycle specifying the address of the register (A[7:0]) whose content must be read. The data bits are don’t care. The device outputs the contents (D[15:0]) of the selected register on the SDOUT pin. For lower-speed SCLKs, SDOUT can be latched on the SCLK rising edge. For higher-speed SCLKs, latching SDOUT at the next SCLK falling edge is preferable. The read operation timing diagram is shown in Figure 101. In readout mode, the REG_READ_EN bit can be accessed with SDIN, SCLK, and SEN. To enable serial register writes, set the REG_READ_EN bit back to 0.

AFE5816 ai_tim_serial_rd_bas623.gif Figure 101. Serial Interface Register, Read Operation

The device SDOUT buffer is 3-stated and is only enabled when the REG_READ_EN bit is enabled. SDOUT pins from multiple devices can therefore be tied together without any pullup resistors. The SN74AUP1T04 level shifter can be used to convert 1.8-V logic to 2.5-V or 3.3-V logic, if necessary.