SBAS688E April   2015  – September 2017 AFE5816

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Family Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: TGC Mode
    6. 8.6  Electrical Characteristics: CW Mode
    7. 8.7  Digital Characteristics
    8. 8.8  Output Interface Timing Requirements
    9. 8.9  Serial Interface Timing Requirements
    10. 8.10 Typical Characteristics: TGC Mode
    11. 8.11 Typical Characteristics: CW Mode
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Attenuator
        1. 9.3.1.1 Implementation
        2. 9.3.1.2 Maximum Signal Amplitude Support
        3. 9.3.1.3 Attenuator High-Pass Filter (ATTEN HPF)
      2. 9.3.2  Low-Noise Amplifier (LNA)
        1. 9.3.2.1 Input Signal Support in TGC Mode
        2. 9.3.2.2 Input Signal Support in CW Mode
        3. 9.3.2.3 Input Circuit
        4. 9.3.2.4 LNA High-Pass Filter (LNA HPF)
          1. 9.3.2.4.1 Disconnecting the LNA HPF During Overload
        5. 9.3.2.5 LNA Noise Contribution
      3. 9.3.3  High-Pass Filter (HPF)
      4. 9.3.4  Low-Pass Filter (LPF)
      5. 9.3.5  Digital TGC (DTGC)
        1. 9.3.5.1 DTGC Overview
        2. 9.3.5.2 DTGC Programming
          1. 9.3.5.2.1 DTGC Profile
            1. 9.3.5.2.1.1 Profile Selection
        3. 9.3.5.3 DTGC Modes
          1. 9.3.5.3.1 Programmable Fixed-Gain Mode
          2. 9.3.5.3.2 Up, Down Ramp Mode
          3. 9.3.5.3.3 External Non-Uniform Mode
          4. 9.3.5.3.4 Internal Non-Uniform Mode
            1. 9.3.5.3.4.1 Memory
              1. 9.3.5.3.4.1.1 Write Operation for the Memory
              2. 9.3.5.3.4.1.2 Read Operation for the Memory
            2. 9.3.5.3.4.2 Gain Curve Description for the Internal Non-Uniform Mode
        4. 9.3.5.4 Timing Specifications
      6. 9.3.6  Continuous-Wave (CW) Beamformer
        1. 9.3.6.1 16 × ƒcw Mode
        2. 9.3.6.2 8 × ƒcw and 4 × ƒcw Modes
        3. 9.3.6.3 1 × ƒcw Mode
        4. 9.3.6.4 CW Clock Selection
        5. 9.3.6.5 CW Supporting Circuits
      7. 9.3.7  Analog-to-Digital Converter (ADC)
        1. 9.3.7.1 System Clock Input
        2. 9.3.7.2 System Clock Configuration for Multiple Devices
      8. 9.3.8  LVDS Interface
        1. 9.3.8.1 LVDS Buffer
        2. 9.3.8.2 LVDS Data Rate Modes
          1. 9.3.8.2.1 1X Data Rate Mode
          2. 9.3.8.2.2 2X Data Rate Mode
      9. 9.3.9  ADC Register, Digital Processing Description
        1. 9.3.9.1 Digital Offset
          1. 9.3.9.1.1 Manual Offset Correction
          2. 9.3.9.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)
        2. 9.3.9.2 Digital Average
        3. 9.3.9.3 Digital Gain
        4. 9.3.9.4 Digital HPF
        5. 9.3.9.5 LVDS Synchronization Operation
      10. 9.3.10 Power Management
        1. 9.3.10.1 Voltage-Controlled Attenuator (VCA) Power Management
        2. 9.3.10.2 Analog-to-Digital Converter (ADC) Power Management
    4. 9.4 Device Functional Modes
      1. 9.4.1 ADC Test Pattern Mode
        1. 9.4.1.1 Test Patterns
          1. 9.4.1.1.1 LVDS Test Pattern Mode
      2. 9.4.2 Partial Power-Up and Power-Down Mode
      3. 9.4.3 Global Power-Down Mode
      4. 9.4.4 TGC Configuration
      5. 9.4.5 Digital TGC Test Modes
        1. 9.4.5.1 ENABLE_INT_START and NEXT_CYCLE_WAIT_TIME
        2. 9.4.5.2 MANUAL_START
        3. 9.4.5.3 FLIP_ATTEN
        4. 9.4.5.4 DIS_ATTEN
        5. 9.4.5.5 Fixed Attenuation Mode
      6. 9.4.6 CW Configuration
      7. 9.4.7 TGC + CW Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Peripheral Interface (SPI) Operation
        1. 9.5.1.1 Serial Register Write Description
        2. 9.5.1.2 Register Readout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
    4. 10.4 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power Sequencing and Initialization
      1. 11.1.1 Power Sequencing
      2. 11.1.2 PLL Initialization
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Supply, Grounding, and Bypassing
      2. 12.1.2 Board Layout
    2. 12.2 Layout Example
  13. 13Register Maps
    1. 13.1 Serial Register Map
      1. 13.1.1 Global Register Map
        1. 13.1.1.1 Description of Global Register
          1. 13.1.1.1.1 Register 0 (address = 0h)
      2. 13.1.2 ADC Register Map
        1. 13.1.2.1 Description of ADC Registers
          1. 13.1.2.1.1  Register 1 (address = 1h)
          2. 13.1.2.1.2  Register 2 (address = 2h)
          3. 13.1.2.1.3  Register 3 (address = 3h)
          4. 13.1.2.1.4  Register 4 (address = 4h)
          5. 13.1.2.1.5  Register 5 (address = 5h)
          6. 13.1.2.1.6  Register 7 (address = 7h)
          7. 13.1.2.1.7  Register 8 (address = 8h)
          8. 13.1.2.1.8  Register 11 (address = Bh)
          9. 13.1.2.1.9  Register 13 (address = Dh)
          10. 13.1.2.1.10 Register 14 (address = Eh)
          11. 13.1.2.1.11 Register 15 (address = Fh)
          12. 13.1.2.1.12 Register 16 (address = 10h)
          13. 13.1.2.1.13 Register 17 (address = 11h)
          14. 13.1.2.1.14 Register 18 (address = 12h)
          15. 13.1.2.1.15 Register 19 (address = 13h)
          16. 13.1.2.1.16 Register 20 (address = 14h)
          17. 13.1.2.1.17 Register 21 (address = 15h)
          18. 13.1.2.1.18 Register 23 (address = 17h)
          19. 13.1.2.1.19 Register 24 (address = 18h)
          20. 13.1.2.1.20 Register 25 (address = 19h)
          21. 13.1.2.1.21 Register 26 (address = 1Ah)
          22. 13.1.2.1.22 Register 27 (address = 1Bh)
          23. 13.1.2.1.23 Register 28 (address = 1Ch)
          24. 13.1.2.1.24 Register 29 (address = 1Dh)
          25. 13.1.2.1.25 Register 30 (address = 1Eh)
          26. 13.1.2.1.26 Register 31 (address = 1Fh)
          27. 13.1.2.1.27 Register 32 (address = 20h)
          28. 13.1.2.1.28 Register 33 (address = 21h)
          29. 13.1.2.1.29 Register 35 (address = 23h)
          30. 13.1.2.1.30 Register 36 (address = 24h)
          31. 13.1.2.1.31 Register 37 (address = 25h)
          32. 13.1.2.1.32 Register 38 (address = 26h)
          33. 13.1.2.1.33 Register 39 (address = 27h)
          34. 13.1.2.1.34 Register 40 (address = 28h)
          35. 13.1.2.1.35 Register 41 (address = 29h)
          36. 13.1.2.1.36 Register 42 (address = 2Ah)
          37. 13.1.2.1.37 Register 43 (address = 2Bh)
          38. 13.1.2.1.38 Register 44 (address = 2Ch)
          39. 13.1.2.1.39 Register 45 (address = 2Dh)
          40. 13.1.2.1.40 Register 47 (address = 2Fh)
          41. 13.1.2.1.41 Register 48 (address = 30h)
          42. 13.1.2.1.42 Register 49 (address = 31h)
          43. 13.1.2.1.43 Register 50 (address = 32h)
          44. 13.1.2.1.44 Register 51 (address = 33h)
          45. 13.1.2.1.45 Register 52 (address = 34h)
          46. 13.1.2.1.46 Register 53 (address = 35h)
          47. 13.1.2.1.47 Register 54 (address = 36h)
          48. 13.1.2.1.48 Register 55 (address = 37h)
          49. 13.1.2.1.49 Register 56 (address = 38h)
          50. 13.1.2.1.50 Register 57 (address = 39h)
          51. 13.1.2.1.51 Register 59 (address = 3Bh)
          52. 13.1.2.1.52 Register 60 (address = 3Ch)
          53. 13.1.2.1.53 Register 65 (address = 41h)
          54. 13.1.2.1.54 Register 66 (address = 42h)
          55. 13.1.2.1.55 Register 67 (address = 43h)
      3. 13.1.3 VCA Register Map
        1. 13.1.3.1 Description of VCA Registers
          1. 13.1.3.1.1  Register 192 (address = C0h)
          2. 13.1.3.1.2  Register 193 (address = C1h)
          3. 13.1.3.1.3  Register 194 (address = C2h)
          4. 13.1.3.1.4  Register 195 (address = C3h)
          5. 13.1.3.1.5  Register 196 (address = C4h)
          6. 13.1.3.1.6  Register 197 (address = C5h)
          7. 13.1.3.1.7  Register 198 (address = C6h)
          8. 13.1.3.1.8  Register 199 (address = C7h)
          9. 13.1.3.1.9  Register 200 (address = C8h)
          10. 13.1.3.1.10 Register 206 (address = CEh)
          11. 13.1.3.1.11 Register 230 (address = E6h)
      4. 13.1.4 DTGC Register Map
        1. 13.1.4.1 Description of DTGC Register
          1. 13.1.4.1.1 DTGC Registers
            1. 13.1.4.1.1.1  Register 1 (address = 1h)
            2. 13.1.4.1.1.2  Registers 2-160 (address = 2h-A0h)
            3. 13.1.4.1.1.3  Register 161 (address = A1h)
            4. 13.1.4.1.1.4  Register 162 (address = A2h)
            5. 13.1.4.1.1.5  Register 163 (address = A3h)
            6. 13.1.4.1.1.6  Register 164 (address = A4h)
            7. 13.1.4.1.1.7  Register 165 (address = A5h)
            8. 13.1.4.1.1.8  Register 166 (address = A6h)
            9. 13.1.4.1.1.9  Register 167 (address = A7h)
            10. 13.1.4.1.1.10 Register 168 (address = A8h)
            11. 13.1.4.1.1.11 Register 169 (address = A9h)
            12. 13.1.4.1.1.12 Register 170 (address = AAh)
            13. 13.1.4.1.1.13 Register 171 (address = ABh)
            14. 13.1.4.1.1.14 Register 172 (address = ACh)
            15. 13.1.4.1.1.15 Register 173 (address = ADh)
            16. 13.1.4.1.1.16 Register 174 (address = AEh)
            17. 13.1.4.1.1.17 Register 175 (address = AFh)
            18. 13.1.4.1.1.18 Register 176 (address = B0h)
            19. 13.1.4.1.1.19 Register 177 (address = B1h)
            20. 13.1.4.1.1.20 Register 178 (address = B2h)
            21. 13.1.4.1.1.21 Register 179 (address = B3h)
            22. 13.1.4.1.1.22 Register 180 (address = B4h)
            23. 13.1.4.1.1.23 Register 181 (address = B5h)
            24. 13.1.4.1.1.24 Register 182 (address = B6h)
            25. 13.1.4.1.1.25 Register 183 (address = B7h)
            26. 13.1.4.1.1.26 Register 185 (address = B9h)
            27. 13.1.4.1.1.27 Register 186 (address = BAh)
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device and Documentation Support

Community Resources

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Trademarks

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Electrostatic Discharge Caution

esds-image

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Glossary

SLYZ022TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.