SBAS688E April 2015 – September 2017 AFE5816
PRODUCTION DATA.
In a mixed-signal system design, the power-supply and grounding design play a significant role. The device distinguishes between two different grounds: AVSS (analog ground) and DVSS (digital ground). In most cases, designing the printed circuit board (PCB) to use a single ground plane is adequate, but in high-frequency or high-performance systems care must be taken so that this ground plane is properly partitioned between various sections within the system to minimize interactions between analog and digital circuitry. Alternatively, the digital supply set consisting of the DVDD_1P8, DVDD_1P2, and DVSS pins can be placed on separate power and ground planes. For this configuration, tie the AVSS and DVSS grounds together at the power connector in a star layout. In addition, optical or digital isolators (such as the ISO7240) can completely separate the analog portion from the digital portion. Consequently, such isolators prevent digital noise from contaminating the analog portion. Table 22 lists the related circuit blocks for each power supply.
POWER SUPPLY | GROUND | CIRCUIT BLOCKS(1) |
---|---|---|
AVDD_3P15 | AVSS | Reference voltage and current generator, LNA, VCNTRL, CW mixer, CW clock buffer, 16 × 16 cross-point switch, and 16-phase generator blocks |
AVDD_1P9 | AVSS | Band-gap circuit, reference voltage and current generator, LNA, PGA, LPF, and VCA SPI blocks |
AVDD_1P8 | AVSS | ADC analog, reference voltage and current generator, band-gap circuit, ADC clock buffer |
DVDD_1P8 | DVSS | LVDS serializer and buffer, and PLL blocks |
DVDD_1P2 | DVSS | ADC digital and serial interface blocks |
Reference all bypassing and power supplies for the device to their corresponding ground planes. Bypass all supply pins with 0.1-μF ceramic chip capacitors (size 0603 or smaller). In order to minimize the lead and trace inductance, the capacitors must be located as close to the supply pins as possible. Where double-sided component mounting is allowed, these capacitors are best placed directly under the package. In addition, larger bipolar decoupling capacitors (2.2 μF to 10 μF, effective at lower frequencies) can also be used on the main supply pins. These components can be placed on the PCB in close proximity (< 0.5 inch or 12.7 mm) to the device itself.
The device has a number of reference supplies that must be bypassed, such as BIAS_2P5, LNA_INCM, BAND_GAP, and SRC_BIAS. Bypass these pins with at least a 1-μF capacitor; higher value capacitors can be used for better low-frequency noise suppression. For best results, choose low-inductance ceramic chip capacitors (size 0402, > 1 μF) placed as close as possible to the device pins.
High-speed, mixed-signal devices are sensitive to various types of noise coupling. One primary source of noise is the switching noise from the serializer and the output buffer and drivers. For the device, care must be taken to ensure that the interaction between the analog and digital supplies within the device is kept to a minimal amount. The extent of noise coupled and transmitted from the digital and analog sections depends on the effective inductances of each supply and ground connection; smaller effective inductances of the supply and ground pins result in better noise suppression. For this reason, multiple pins are used to connect each supply and ground set. Low inductance properties must be maintained throughout the design of the PCB layout by the use of proper planes and layer thickness.
To avoid noise coupling through supply pins, keep sensitive input pins (such as the INM and INP pins) away from the AVDD_3P15 and AVDD_1P9 planes. For example, do not route the traces or vias connected to these pins across the AVDD_3P15 and AVDD_1P9 planes. That is, avoid the power planes under the INM and INP pins.
In order to maintain proper LVDS timing, all LVDS traces must follow a controlled impedance design. In addition, all LVDS trace lengths must be equal and symmetrical; keep trace length variations less than 150 mil (0.150 inch or 3.81 mm).
In addition, appropriate delay matching must be considered for the CW clock path, especially in systems with a high channel count. For example, if the clock delay is half of the 16X clock period, a phase error of 22.5°C can exist. Thus, the timing delay difference among channels contributes to the beamformer accuracy.
Additional details on the NFBGA PCB layout techniques can be found in the Texas Instruments application report SSYZ015 that can be downloaded from www.ti.com.
Figure 107 and Figure 108 illustrate example layouts for the top and bottom layers, respectively.
Figure 109 shows the routing of input traces and differential CW outputs.
Figure 110 shows routing examples for different power planes.
Figure 111, Figure 112, and Figure 113 illustrate routing examples for different power planes.