SBAS688E April   2015  – September 2017 AFE5816

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Family Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: TGC Mode
    6. 8.6  Electrical Characteristics: CW Mode
    7. 8.7  Digital Characteristics
    8. 8.8  Output Interface Timing Requirements
    9. 8.9  Serial Interface Timing Requirements
    10. 8.10 Typical Characteristics: TGC Mode
    11. 8.11 Typical Characteristics: CW Mode
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Attenuator
        1. 9.3.1.1 Implementation
        2. 9.3.1.2 Maximum Signal Amplitude Support
        3. 9.3.1.3 Attenuator High-Pass Filter (ATTEN HPF)
      2. 9.3.2  Low-Noise Amplifier (LNA)
        1. 9.3.2.1 Input Signal Support in TGC Mode
        2. 9.3.2.2 Input Signal Support in CW Mode
        3. 9.3.2.3 Input Circuit
        4. 9.3.2.4 LNA High-Pass Filter (LNA HPF)
          1. 9.3.2.4.1 Disconnecting the LNA HPF During Overload
        5. 9.3.2.5 LNA Noise Contribution
      3. 9.3.3  High-Pass Filter (HPF)
      4. 9.3.4  Low-Pass Filter (LPF)
      5. 9.3.5  Digital TGC (DTGC)
        1. 9.3.5.1 DTGC Overview
        2. 9.3.5.2 DTGC Programming
          1. 9.3.5.2.1 DTGC Profile
            1. 9.3.5.2.1.1 Profile Selection
        3. 9.3.5.3 DTGC Modes
          1. 9.3.5.3.1 Programmable Fixed-Gain Mode
          2. 9.3.5.3.2 Up, Down Ramp Mode
          3. 9.3.5.3.3 External Non-Uniform Mode
          4. 9.3.5.3.4 Internal Non-Uniform Mode
            1. 9.3.5.3.4.1 Memory
              1. 9.3.5.3.4.1.1 Write Operation for the Memory
              2. 9.3.5.3.4.1.2 Read Operation for the Memory
            2. 9.3.5.3.4.2 Gain Curve Description for the Internal Non-Uniform Mode
        4. 9.3.5.4 Timing Specifications
      6. 9.3.6  Continuous-Wave (CW) Beamformer
        1. 9.3.6.1 16 × ƒcw Mode
        2. 9.3.6.2 8 × ƒcw and 4 × ƒcw Modes
        3. 9.3.6.3 1 × ƒcw Mode
        4. 9.3.6.4 CW Clock Selection
        5. 9.3.6.5 CW Supporting Circuits
      7. 9.3.7  Analog-to-Digital Converter (ADC)
        1. 9.3.7.1 System Clock Input
        2. 9.3.7.2 System Clock Configuration for Multiple Devices
      8. 9.3.8  LVDS Interface
        1. 9.3.8.1 LVDS Buffer
        2. 9.3.8.2 LVDS Data Rate Modes
          1. 9.3.8.2.1 1X Data Rate Mode
          2. 9.3.8.2.2 2X Data Rate Mode
      9. 9.3.9  ADC Register, Digital Processing Description
        1. 9.3.9.1 Digital Offset
          1. 9.3.9.1.1 Manual Offset Correction
          2. 9.3.9.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)
        2. 9.3.9.2 Digital Average
        3. 9.3.9.3 Digital Gain
        4. 9.3.9.4 Digital HPF
        5. 9.3.9.5 LVDS Synchronization Operation
      10. 9.3.10 Power Management
        1. 9.3.10.1 Voltage-Controlled Attenuator (VCA) Power Management
        2. 9.3.10.2 Analog-to-Digital Converter (ADC) Power Management
    4. 9.4 Device Functional Modes
      1. 9.4.1 ADC Test Pattern Mode
        1. 9.4.1.1 Test Patterns
          1. 9.4.1.1.1 LVDS Test Pattern Mode
      2. 9.4.2 Partial Power-Up and Power-Down Mode
      3. 9.4.3 Global Power-Down Mode
      4. 9.4.4 TGC Configuration
      5. 9.4.5 Digital TGC Test Modes
        1. 9.4.5.1 ENABLE_INT_START and NEXT_CYCLE_WAIT_TIME
        2. 9.4.5.2 MANUAL_START
        3. 9.4.5.3 FLIP_ATTEN
        4. 9.4.5.4 DIS_ATTEN
        5. 9.4.5.5 Fixed Attenuation Mode
      6. 9.4.6 CW Configuration
      7. 9.4.7 TGC + CW Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Peripheral Interface (SPI) Operation
        1. 9.5.1.1 Serial Register Write Description
        2. 9.5.1.2 Register Readout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
    4. 10.4 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power Sequencing and Initialization
      1. 11.1.1 Power Sequencing
      2. 11.1.2 PLL Initialization
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Supply, Grounding, and Bypassing
      2. 12.1.2 Board Layout
    2. 12.2 Layout Example
  13. 13Register Maps
    1. 13.1 Serial Register Map
      1. 13.1.1 Global Register Map
        1. 13.1.1.1 Description of Global Register
          1. 13.1.1.1.1 Register 0 (address = 0h)
      2. 13.1.2 ADC Register Map
        1. 13.1.2.1 Description of ADC Registers
          1. 13.1.2.1.1  Register 1 (address = 1h)
          2. 13.1.2.1.2  Register 2 (address = 2h)
          3. 13.1.2.1.3  Register 3 (address = 3h)
          4. 13.1.2.1.4  Register 4 (address = 4h)
          5. 13.1.2.1.5  Register 5 (address = 5h)
          6. 13.1.2.1.6  Register 7 (address = 7h)
          7. 13.1.2.1.7  Register 8 (address = 8h)
          8. 13.1.2.1.8  Register 11 (address = Bh)
          9. 13.1.2.1.9  Register 13 (address = Dh)
          10. 13.1.2.1.10 Register 14 (address = Eh)
          11. 13.1.2.1.11 Register 15 (address = Fh)
          12. 13.1.2.1.12 Register 16 (address = 10h)
          13. 13.1.2.1.13 Register 17 (address = 11h)
          14. 13.1.2.1.14 Register 18 (address = 12h)
          15. 13.1.2.1.15 Register 19 (address = 13h)
          16. 13.1.2.1.16 Register 20 (address = 14h)
          17. 13.1.2.1.17 Register 21 (address = 15h)
          18. 13.1.2.1.18 Register 23 (address = 17h)
          19. 13.1.2.1.19 Register 24 (address = 18h)
          20. 13.1.2.1.20 Register 25 (address = 19h)
          21. 13.1.2.1.21 Register 26 (address = 1Ah)
          22. 13.1.2.1.22 Register 27 (address = 1Bh)
          23. 13.1.2.1.23 Register 28 (address = 1Ch)
          24. 13.1.2.1.24 Register 29 (address = 1Dh)
          25. 13.1.2.1.25 Register 30 (address = 1Eh)
          26. 13.1.2.1.26 Register 31 (address = 1Fh)
          27. 13.1.2.1.27 Register 32 (address = 20h)
          28. 13.1.2.1.28 Register 33 (address = 21h)
          29. 13.1.2.1.29 Register 35 (address = 23h)
          30. 13.1.2.1.30 Register 36 (address = 24h)
          31. 13.1.2.1.31 Register 37 (address = 25h)
          32. 13.1.2.1.32 Register 38 (address = 26h)
          33. 13.1.2.1.33 Register 39 (address = 27h)
          34. 13.1.2.1.34 Register 40 (address = 28h)
          35. 13.1.2.1.35 Register 41 (address = 29h)
          36. 13.1.2.1.36 Register 42 (address = 2Ah)
          37. 13.1.2.1.37 Register 43 (address = 2Bh)
          38. 13.1.2.1.38 Register 44 (address = 2Ch)
          39. 13.1.2.1.39 Register 45 (address = 2Dh)
          40. 13.1.2.1.40 Register 47 (address = 2Fh)
          41. 13.1.2.1.41 Register 48 (address = 30h)
          42. 13.1.2.1.42 Register 49 (address = 31h)
          43. 13.1.2.1.43 Register 50 (address = 32h)
          44. 13.1.2.1.44 Register 51 (address = 33h)
          45. 13.1.2.1.45 Register 52 (address = 34h)
          46. 13.1.2.1.46 Register 53 (address = 35h)
          47. 13.1.2.1.47 Register 54 (address = 36h)
          48. 13.1.2.1.48 Register 55 (address = 37h)
          49. 13.1.2.1.49 Register 56 (address = 38h)
          50. 13.1.2.1.50 Register 57 (address = 39h)
          51. 13.1.2.1.51 Register 59 (address = 3Bh)
          52. 13.1.2.1.52 Register 60 (address = 3Ch)
          53. 13.1.2.1.53 Register 65 (address = 41h)
          54. 13.1.2.1.54 Register 66 (address = 42h)
          55. 13.1.2.1.55 Register 67 (address = 43h)
      3. 13.1.3 VCA Register Map
        1. 13.1.3.1 Description of VCA Registers
          1. 13.1.3.1.1  Register 192 (address = C0h)
          2. 13.1.3.1.2  Register 193 (address = C1h)
          3. 13.1.3.1.3  Register 194 (address = C2h)
          4. 13.1.3.1.4  Register 195 (address = C3h)
          5. 13.1.3.1.5  Register 196 (address = C4h)
          6. 13.1.3.1.6  Register 197 (address = C5h)
          7. 13.1.3.1.7  Register 198 (address = C6h)
          8. 13.1.3.1.8  Register 199 (address = C7h)
          9. 13.1.3.1.9  Register 200 (address = C8h)
          10. 13.1.3.1.10 Register 206 (address = CEh)
          11. 13.1.3.1.11 Register 230 (address = E6h)
      4. 13.1.4 DTGC Register Map
        1. 13.1.4.1 Description of DTGC Register
          1. 13.1.4.1.1 DTGC Registers
            1. 13.1.4.1.1.1  Register 1 (address = 1h)
            2. 13.1.4.1.1.2  Registers 2-160 (address = 2h-A0h)
            3. 13.1.4.1.1.3  Register 161 (address = A1h)
            4. 13.1.4.1.1.4  Register 162 (address = A2h)
            5. 13.1.4.1.1.5  Register 163 (address = A3h)
            6. 13.1.4.1.1.6  Register 164 (address = A4h)
            7. 13.1.4.1.1.7  Register 165 (address = A5h)
            8. 13.1.4.1.1.8  Register 166 (address = A6h)
            9. 13.1.4.1.1.9  Register 167 (address = A7h)
            10. 13.1.4.1.1.10 Register 168 (address = A8h)
            11. 13.1.4.1.1.11 Register 169 (address = A9h)
            12. 13.1.4.1.1.12 Register 170 (address = AAh)
            13. 13.1.4.1.1.13 Register 171 (address = ABh)
            14. 13.1.4.1.1.14 Register 172 (address = ACh)
            15. 13.1.4.1.1.15 Register 173 (address = ADh)
            16. 13.1.4.1.1.16 Register 174 (address = AEh)
            17. 13.1.4.1.1.17 Register 175 (address = AFh)
            18. 13.1.4.1.1.18 Register 176 (address = B0h)
            19. 13.1.4.1.1.19 Register 177 (address = B1h)
            20. 13.1.4.1.1.20 Register 178 (address = B2h)
            21. 13.1.4.1.1.21 Register 179 (address = B3h)
            22. 13.1.4.1.1.22 Register 180 (address = B4h)
            23. 13.1.4.1.1.23 Register 181 (address = B5h)
            24. 13.1.4.1.1.24 Register 182 (address = B6h)
            25. 13.1.4.1.1.25 Register 183 (address = B7h)
            26. 13.1.4.1.1.26 Register 185 (address = B9h)
            27. 13.1.4.1.1.27 Register 186 (address = BAh)
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Register Maps

Serial Register Map

The device is a multichip module (MCM) with two dies: the VCA die and the ADC_CONV die, as shown in Figure 114. Figure 114 also describes the channel mapping of the VCA die to the input pins. Both dies share the same SPI control signals (SCLK, SDIN, and SEN).

AFE5816 ai_channel_map_vca_bas641.gif Figure 114. Channel Mapping: VCA Dies

A reset process is required at the device initialization stage.

NOTE

Initialization can be accomplished with a hardware reset by applying a positive pulse to the RESET pin. After reset, all ADC and VCA registers are set to default values. Note that during register programming, all unnamed register bits must be set to 0 for the register that is being programmed.

The device consists of the following register maps:

  1. Global register map. This register map is common to both the ADC_CONV and VCA dies. The global register map consists of register 0. To program the global register map, set the DTGC_WR_EN bit to 0.
  2. ADC register map. This register map programs the ADC die. The ADC register map consists of register 1 to register 67. To program the ADC register map, set the DTGC_WR_EN bit to 0.
  3. VCA register map. This register map contains register 192 to register 230 and programs all VCA blocks except the DTGC engine. To program the VCA register map, set the DTGC_WR_EN bit to 0.
  4. DTGC register map. This register map contains register 1 to register 186 and programs the TGC control engine of the VCA die. To program the DTGC register map, set the DTGC_WR_EN bit to 1.

Because these register maps share the same address space, the DTGC_WR_EN bit is used to program the different register maps, as listed in Table 23.

Table 23. Register Configuration

REGISTER MAP ADDRESS DTGC_WR_EN BIT
Global register map 0 0
ADC register map 1 to 67 0
VCA register map 192 to 230 0
DTGC register map 1 to 186 1

Global Register Map

This section discusses the global register. This register map is shown in Table 24.

DTGC_WR_EN must be set to 0 before programming other bits of the global register map.

Table 24. Global Register Map

REGISTER ADDRESS REGISTER DATA(1)
DECIMAL HEX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 DTGC_
WR_EN
0 0 REG_READ_
EN
SOFTWARE_
RESET
The default value of all registers is 0.

Description of Global Register

Register 0 (address = 0h)

Figure 115. Register 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
0 0 0 DTGC_WR_EN 0 0 REG_READ_
EN
SOFTWARE_
RESET
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: W = Write only; -n = value

Table 25. Register 0 Field Descriptions

Bit Field Type Reset Description
15-5 0 W 0h Must write 0
4 DTGC_WR_EN W 0h 0 = Enables programming of the global, ADC, and VCA register maps
1 = Enables programming of the DTGC register map
3-2 0 W 0h Must write 0
1 REG_READ_EN W 0h 0 = Register readout mode disabled
1 = Register readout mode enabled
0 SOFTWARE_RESET W 0h 0 = Disabled
1 = Enabled (this setting returns the device to a reset state). This bit is a self-clearing register bit.

ADC Register Map

This section discusses the ADC register map. A register map is available in Table 26.

DTGC_WR_EN must be set to 0 before programming the ADC register map.

Table 26. ADC Register Map

REGISTER ADDRESS REGISTER DATA(1)
DECIMAL HEX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 LVDS_
RATE_2X
0 0 0 0 0 0 0 0 DIS_LVDS 1 0 1 0 GLOBAL_
PDN
2 2 PAT_MODES_FCLK[2:0] LOW_
LATENCY_EN
AVG_EN SEL_PRBS_PAT_
FCLK
PAT_MODES[2:0] SEL_PRBS_PAT_GBL OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0]
3 3 SER_DATA_RATE DIG_GAIN_EN 0 OFFSET_CORR_DELAY_FROM_TX_TRIG[7:6] DIG_
OFFSET_
EN
0 0 0 0 0 0 0 0
4 4 OFFSET_
REMOVAL_SELF
OFFSET_
REMOVAL_START_
SEL
OFFEST_
REMOVAL_START_
MANUAL
AUTO_OFFSET_REMOVAL_ACC_CYCLES[3:0] PAT_
SELECT_
IND
PRBS_
SYNC
PRBS_
MODE
PRBS_EN MSB_
FIRST
0 0 ADC_RES
5 5 CUSTOM_PATTERN[15:0]
7 7 AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL[4:0] 0 0 0 0 0 0 0 0 0 0 CHOPPER_EN
8 8 0 0 AUTO_OFFSET_REMOVAL_VAL_RD[13:0]
11 B 0 0 0 0 EN_
DITHER
0 0 0 0 0 0 0 0 0 0 0
13 D GAIN_CH1 0 OFFSET_CH1
14 E 0 0 OFFSET_CH1
15 F GAIN_CH2 0 OFFSET_CH2
16 10 0 0 OFFSET_CH2
17 11 GAIN_CH3 0 OFFSET_CH3
18 12 0 0 OFFSET_CH3
19 13 GAIN_CH4 0 OFFSET_CH4
20 14 0 0 OFFSET_CH4
21 15 PAT_PRBS_LVDS1 PAT_PRBS_LVDS2 PAT_PRBS_LVDS3 PAT_PRBS_LVDS4 PAT_LVDS1[2:0] PAT_LVDS2[2:0] HPF_
ROUND_
EN_CH1-8
HPF_CORNER_CH1-4[3:0] DIG_HPF_
EN_CH1-4
23 17 0 0 0 0 0 0 0 0 PAT_LVDS3[2:0] PAT_LVDS4[2:0] 0 0
24 18 PDN_DIG_CH4 PDN_DIG_CH3 PDN_DIG_CH2 PDN_DIG_CH1 PDN_
LVDS4
PDN_
LVDS3
PDN_
LVDS2
PDN_
LVDS1
PDN_ANA_CH4 PDN_ANA_CH3 PDN_ANA_CH2 PDN_ANA_CH1 INVERT_
CH4
INVERT_
CH3
INVERT_
CH2
INVERT_
CH1
25 19 GAIN_CH5 0 OFFSET_CH5
26 1A 0 0 OFFSET_CH5
27 1B GAIN_CH6 0 OFFSET_CH6
28 1C 0 0 OFFSET_CH6
29 1D GAIN_CH7 0 OFFSET_CH7
30 1E 0 0 OFFSET_CH7
31 1F GAIN_CH8 0 OFFSET_CH8
32 20 0 0 OFFSET_CH8
33 21 PAT_PRBS_LVDS5 PAT_PRBS_LVDS6 PAT_PRBS_LVDS7 PAT_PRBS_LVDS8 PAT_LVDS5[2:0] PAT_LVDS6[2:0] 0 HPF_CORNER_CH5-8[3:0] DIG_HPF_
EN_CH5-8
35 23 0 0 0 0 0 0 0 0 PAT_LVDS7[2:0] PAT_LVDS8[2:0] 0 0
36 24 PDN_DIG_CH8 PDN_DIG_CH7 PDN_DIG_CH6 PDN_DIG_CH5 PDN_
LVDS8
PDN_
LVDS7
PDN_
LVDS6
PDN_
LVDS5
PDN_ANA_CH8 PDN_ANA_CH7 PDN_ANA_CH6 PDN_ANA_CH5 INVERT_
CH8
INVERT_
CH7
INVERT_
CH6
INVERT_
CH5
37 25 GAIN_CH9 0 OFFSET_CH9
38 26 0 0 OFFSET_CH9
39 27 GAIN_CH10 0 OFFSET_CH10
40 28 0 0 OFFSET_CH10
41 29 GAIN_CH11 0 OFFSET_CH11
42 2A 0 0 OFFSET_CH11
43 2B GAIN_CH12 0 OFFSET_CH12
44 2C 0 0 OFFSET_CH12
45 2D PAT_PRBS_LVDS9 PAT_PRBS_LVDS10 PAT_PRBS_LVDS11 PAT_PRBS_LVDS12 PAT_LVDS9[2:0] PAT_LVDS10[2:0] HPF_ROUND_EN_CH1-8 HPF_CORNER_CH9-12[3:0] DIG_HPF_
EN_
CH9-12
47 2F 0 0 0 0 0 0 0 0 PAT_LVDS11[2:0] PAT_LVDS12[2:0] 0 0
48 30 PDN_DIG_CH12 PDN_DIG_CH11 PDN_DIG_CH10 PDN_DIG_CH9 PDN_
LVDS12
PDN_
LVDS11
PDN_
LVDS10
PDN_
LVDS9
PDN_ANA_CH12 PDN_ANA_CH11 PDN_ANA_CH10 PDN_ANA_CH9 INVERT_
CH12
INVERT_
CH11
INVERT_
CH10
INVERT_
CH9
49 31 GAIN_CH13 0 OFFSET_CH13
50 32 0 0 OFFSET_CH13
51 33 GAIN_CH14 0 OFFSET_CH14
52 34 0 0 OFFSET_CH14
53 35 GAIN_CH15 0 OFFSET_CH15
54 36 0 0 OFFSET_CH15
55 37 GAIN_CH16 0 OFFSET_CH16
56 38 0 0 OFFSET_CH16
57 39 PAT_PRBS_LVDS13 PAT_PRBS_LVDS14 PAT_PRBS_LVDS15 PAT_PRBS_LVDS16 PAT_LVDS13[2:0] PAT_LVDS14[2:0] 0 HPF_CORNER_CH13-16[3:0] DIG_HPF_
EN_
CH13-16
59 3B 0 0 0 0 0 0 0 0 PAT_LVDS15[2:0] PAT_LVDS16[2:0] 0 0
60 3C PDN_DIG_CH16 PDN_DIG_CH15 PDN_DIG_CH14 PDN_DIG_CH13 PDN_
LVDS16
PDN_
LVDS15
PDN_
LVDS14
PDN_
LVDS13
PDN_ANA_CH16 PDN_ANA_CH15 PDN_ANA_CH14 PDN_ANA_CH13 INVERT_
CH16
INVERT_
CH15
INVERT_
CH14
INVERT_
CH13
65 41 PLLRST1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
66 42 PLLRST2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
67 43 0 0 0 0 0 0 0 0 0 0 0 LVDS_DCLK_DELAY_PROG[3:0] 0
Default value of all registers is 0.

Description of ADC Registers

Register 1 (address = 1h)

Figure 116. Register 1
15 14 13 12 11 10 9 8
0 LVDS_RATE_
2X
0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 DIS_LVDS 1 0 1 0 GLOBAL_PDN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 27. Register 1 Field Descriptions

Bit Field Type Reset Description
15 0 R/W 0h Must write 0
14 LVDS_RATE_2X R/W 0h 0 = 1X rate; normal operation (default)
1 = 2X rate. This setting combines the data of two LVDS pairs into a single LVDS pair. This feature can be used when the ADC clock rate is low; see the LVDS Interface section for further details.
13-6 0 R/W 0h Must write 0
5 DIS_LVDS R/W 0h 0 = LVDS interface is enabled (default)
1 = LVDS interface is disabled
4 1 R/W 0h Must write 1
3 0 R/W 0h Must write 0
2 1 R/W 0h Must write 1
1 0 R/W 0h Must write 0
0 GLOBAL_PDN R/W 0h 0 = Device operates in normal mode (default)
1 = ADC enters complete power-down mode

Register 2 (address = 2h)

Figure 117. Register 2
15 14 13 12 11 10 9 8
PAT_MODES_FCLK[2:0] LOW_
LATENCY_EN
AVG_EN SEL_PRBS_
PAT_FCLK
PAT_MODES[2:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PAT_
MODES[2:0]
SEL_PRBS_
PAT_GBL
OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0]
R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 28. Register 2 Field Descriptions

Bit Field Type Reset Description
15-13 PAT_MODES_FCLK[2:0] R/W 0h These bits enable different test patterns on the frame clock line; see Table 29 for bit descriptions and the Test Patterns section for further details.
12 LOW_LATENCY_EN R/W 0h 0 = Default latency with digital features supported
1 = Low latency with digital features bypassed
11 AVG_EN R/W 0h 0 = No averaging
1 = Enables averaging of two channels to improve signal-to-noise ratio (SNR); see the LVDS Interface section for further details.
10 SEL_PRBS_PAT_FCLK R/W 0h 0 = Normal operation
1 = Enables the PRBS pattern to be generated on fCLK; see the Test Patterns section for further details
9-7 PAT_MODES[2:0] R/W 0h These bits enable different test patterns on the LVDS data lines; see Table 29 for bit descriptions and the Test Patterns section for further details.
6 SEL_PRBS_PAT_GBL R/W 0h 0 = Normal operation
1 = Enables the PRBS pattern to be generated; see the Test Patterns section for further details
5-0 OFFSET_CORR_DELAY_
FROM_TX_TRIG[5:0]
R/W 0h This 8-bit register initiates an offset correction after the TX_TRIG input pulse (each step is equivalent to one sample delay); the remaining two MSB bits are the OFFSET_CORR_DELAY_FROM_TX_TRIG[7:6] bits (bits 10-9) in register 3.

Table 29. Pattern Mode Bit Description

PAT_MODES[2:0] DESCRIPTION
000 Normal operation
001 Sync (half frame 1, half frame 0)
010 Alternate 0s and 1s
011 Custom pattern(1)
100 All 1s
101 Toggle mode
110 All 0s
111 Ramp pattern(1)
Either the custom or the ramp pattern setting is required for PRBS pattern selection.

Register 3 (address = 3h)

Figure 118. Register 3
15 14 13 12 11 10 9 8
SER_DATA_RATE DIG_GAIN_EN 0 OFFSET_CORR_DELAY_FROM_TX_TRIG[7:6] DIG_
OFFSET_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 30. Register 3 Field Descriptions

Bit Field Type Reset Description
15-13 SER_DATA_RATE R/W 0h These bits control the LVDS serialization rate.
000 = 12X
001 = 14X
100 = 16X
101, 110, 111, 010, 011 = Unused
12 DIG_GAIN_EN R/W 0h 0 = Digital gain disabled
1 = Digital gain enabled
11 0 R/W 0h Must write 0
10-9 OFFSET_CORR_DELAY_
FROM_TX_TRIG[7:6]
R/W 0h This 8-bit register initiates an offset correction after the TX_TRIG input pulse (each step is equivalent to one sample delay); the remaining six LSB bits are the OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0] bits (bits 5-0) in register 2.
8 DIG_OFFSET_EN R/W 0h 0 = Digital offset subtraction disabled
1 = Digital offset subtraction enabled
7-0 0 R/W 0h Must write 0

Register 4 (address = 4h)

Figure 119. Register 4
15 14 13 12 11 10 9 8
OFFSET_REMOVAL_SELF OFFSET_REMOVAL_START_SEL OFFSET_REMOVAL_START_ MANUAL AUTO_OFFSET_REMOVAL_ACC_CYCLES PAT_
SELECT_IND
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PRBS_
SYNC
PRBS_
MODE
PRBS_EN MSB_FIRST 0 0 ADC_RES
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 31. Register 4 Field Descriptions

Bit Field Type Reset Description
15 OFFSET_REMOVAL_SELF R/W 0h 0 = Auto offset correction mode is enabled
1 = Offset correction via register is enabled
14 OFFSET_REMOVAL_START_SEL R/W 0h 0 = Auto offset correction is initiated when the OFFSET_REMOVAL_START_MANUAL bit is set to 1
1 = Auto offset correction is initiated with a pulse on the TX_TRIG pin
13 OFFSET_REMOVAL_START_
MANUAL
R/W 0h This bit initiates an offset correction manually instead of with a TX_TRIG pulse
12-9 AUTO_OFFSET_REMOVAL_
ACC_CYCLES
R/W 0h These bits define the number of samples required to generate an offset in auto offset correction mode
8 PAT_SELECT_IND R/W 0h 0 = All LVDS output lines have the same pattern, as determined by the PAT_MODES[2:0] bits
1 = Different test patterns can be sent on different LVDS lines, depending upon the channel and register; see the Test Patterns section for further details
7 PRBS_SYNC R/W 0h 0 = Normal operation
1 = PRBS generator is in a reset state
6 PRBS_MODE R/W 0h 0 = 23-bit PRBS generator
1 = 9-bit PRBS generator
5 PRBS_EN R/W 0h 0 = PRBS sequence generation block disabled
1 = PRBS sequence generation block enabled; see the Test Patterns section for further details
4 MSB_FIRST R/W 0h 0 = The LSB is transmitted first on serialized output data
1 = The MSB is transmitted first on serialized output data
3 0 R/W 0h Must write 0
2 0 R/W 0h Must write 0
1-0 ADC_RES R/W 0h These bits control the ADC resolution.
00 = 12-bit resolution
01 = 14-bit resolution
10, 11 = Unused

Register 5 (address = 5h)

Figure 120. Register 5
15 14 13 12 11 10 9 8
CUSTOM_PATTERN[15:0]
R/W-0h
7 6 5 4 3 2 1 0
CUSTOM_PATTERN[13:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 32. Register 5 Field Descriptions

Bit Field Type Reset Description
15-0 CUSTOM_PATTERN[15:0] R/W 0h If the pattern mode is programmed to a custom pattern mode, then the custom pattern value can be provided by programming these bits; see the Test Patterns section for further details.

Register 7 (address = 7h)

Figure 121. Register 7
15 14 13 12 11 10 9 8
AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 CHOPPER_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 33. Register 7 Field Descriptions

Bit Field Type Reset Description
15-11 AUTO_OFFSET_REMOVAL_
VAL_RD_CH_SEL
R/W 0h Write the channel number to read the offset value in auto offset correction mode for a corresponding channel number (read the offset value in register 8, bits 13-0)
10-1 0 R/W 0h Must write 0
0 CHOPPER_EN R/W 0h The chopper can be used to move low-frequency, 1 / f noise to an fS / 2 frequency.
0 = Chopper disabled
1 = Chopper enabled

Register 8 (address = 8h)

Figure 122. Register 8
15 14 13 12 11 10 9 8
0 0 AUTO_OFFSET_REMOVAL_VAL_RD[13:0]
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
AUTO_OFFSET_REMOVAL_VAL_RD[13:0]
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 34. Register 8 Field Descriptions

Bit Field Type Reset Description
15-14 0 R/W 0h Must write 0
13-0 AUTO_OFFSET_REMOVAL_VAL_RD R/W 0h Read the offset value applied in auto offset correction mode for a specific channel number as defined in the AUTO_OFFSET_REMOVAL_VAL_RD_CH_SEL[4:0] register bit.

Register 11 (address = Bh)

Figure 123. Register 11
15 14 13 12 11 10 9 8
0 0 0 0 EN_DITHER 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 35. Register 11 Field Descriptions

Bit Field Type Reset Description
15-12 0 R/W 0h Must write 0
11 EN_DITHER R/W 0h Dither can be used to remove higher-order harmonics.
0 = Dither disabled
1 = Dither enabled
Note: Enabling the dither converts higher-order harmonics power in noise. Thus, enabling this mode removes harmonics but degrades SNR.
10-0 0 R/W 0h Must write 0

Register 13 (address = Dh)

Figure 124. Register 13
15 14 13 12 11 10 9 8
GAIN_CH1 0 OFFSET_CH1
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 36. Register 13 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH1 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 1 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH1 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 1 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 14, bits 9-0.

Register 14 (address = Eh)

Figure 125. Register 14
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 37. Register 14 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH1 R/W 0h When the DIG_OFFSET_EN bit is set to 1, then the offset value for channel 1 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 13, bits 9-0.

Register 15 (address = Fh)

Figure 126. Register 15
15 14 13 12 11 10 9 8
GAIN_CH2 0 OFFSET_CH2
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 38. Register 15 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH2 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 2 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH2 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 2 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 16, bits 9-0.

Register 16 (address = 10h)

Figure 127. Register 16
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH2
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 39. Register 16 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH2 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 2 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 15, bits 9-0.

Register 17 (address = 11h)

Figure 128. Register 17
15 14 13 12 11 10 9 8
GAIN_CH3 0 OFFSET_CH3
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH3
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 40. Register 17 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH3 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 3 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH3 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 3 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 18, bits 9-0.

Register 18 (address = 12h)

Figure 129. Register 18
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH3
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH3
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 41. Register 18 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH3 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 3 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 17, bits 9-0.

Register 19 (address = 13h)

Figure 130. Register 19
15 14 13 12 11 10 9 8
GAIN_CH4 0 OFFSET_CH4
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH4
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 42. Register 19 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH4 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 4 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH4 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 4 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 20, bits 9-0.

Register 20 (address = 14h)

Figure 131. Register 20
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH4
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH4
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 43. Register 20 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH4 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 4 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 19, bits 9-0.

Register 21 (address = 15h)

Figure 132. Register 21
15 14 13 12 11 10 9 8
PAT_PRBS_
LVDS1
PAT_PRBS_
LVDS2
PAT_PRBS_
LVDS3
PAT_PRBS_
LVDS4
PAT_LVDS1[2:0] PAT_
LVDS2[2:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PAT_LVDS2[2:0] HPF_ROUND_EN_CH1-8 HPF_CORNER_CH1-4[3:0] DIG_HPF_EN_CH1-4
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 44. Register 21 Field Descriptions

Bit Field Type Reset Description
15 PAT_PRBS_LVDS1 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 1 can be enabled with this bit; see the Test Patterns section for further details.
14 PAT_PRBS_LVDS2 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 2 can be enabled with this bit; see the Test Patterns section for further details.
13 PAT_PRBS_LVDS3 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 3 can be enabled with this bit; see the Test Patterns section for further details.
12 PAT_PRBS_LVDS4 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 4 can be enabled with this bit; see the Test Patterns section for further details.
11-9 PAT_LVDS1[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 1 can be programmed with these bits; see Table 45 for bit descriptions.
8-6 PAT_LVDS2[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 2 can be programmed with these bits; see Table 45 for bit descriptions.
5 HPF_ROUND_EN_CH1-8 R/W 0h 0 = Rounding in the ADC HPF is disabled for channel 1 to 8. HPF output is truncated to be mapped to the ADC resolution bits.
1 = HPF output of channel 1 to 8 is mapped to the ADC resolution bits by the round-off operation.
4-1 HPF_CORNER_CH1-4[3:0] R/W 0h When the DIG_HPF_EN_CH1-4 bit is set to 1, the digital HPF characteristic for the corresponding channels can be programmed by setting the value of k with these bits. Characteristics of a digital high-pass transfer function applied to the output data for a given value of k is defined by:
AFE5816 q_yn_bas623.gif
Note that the value of k can be from 2 to 10 (0010b to 1010b); see the Digital HPF section for further details.
0 DIG_HPF_EN_CH1-4 R/W 0h 0 = Digital HPF disabled for channels 1 to 4 (default)
1 = Enables digital HPF for channels 1 to 4

Table 45. Pattern Mode Bit Description

PAT_MODES[2:0] DESCRIPTION
000 Normal operation
001 Sync (half frame 0, half frame 1)
010 Alternate 0s and 1s
011 Custom pattern
100 All 1s
101 Toggle mode
110 All 0s
111 Ramp pattern

Register 23 (address = 17h)

Figure 133. Register 23
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PAT_LVDS3[2:0] PAT_LVDS4[2:0] 0 0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 46. Register 23 Field Descriptions

Bit Field Type Reset Description
15-8 0 R/W 0h Must write 0
7-5 PAT_LVDS3[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 3 can be programmed with these bits; see Table 45 for bit descriptions.
4-2 PAT_LVDS4[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 4 can be programmed with these bits; see Table 45 for bit descriptions.
1-0 0 R/W 0h Must write 0

Register 24 (address = 18h)

Figure 134. Register 24
15 14 13 12 11 10 9 8
PDN_DIG_
CH4
PDN_DIG_
CH3
PDN_DIG_
CH2
PDN_DIG_
CH1
PDN_LVDS4 PDN_LVDS3 PDN_LVDS2 PDN_LVDS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PDN_ANA_
CH4
PDN_ANA_
CH3
PDN_ANA_
CH2
PDN_ANA_
CH1
INVERT_
CH4
INVERT_
CH3
INVERT_
CH2
INVERT_
CH1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 47. Register 24 Field Descriptions

Bit Field Type Reset Description
15 PDN_DIG_CH4 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 4
14 PDN_DIG_CH3 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 3
13 PDN_DIG_CH2 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel2
12 PDN_DIG_CH1 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 1
11 PDN_LVDS4 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 4
10 PDN_LVDS3 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 3
9 PDN_LVDS2 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 2
8 PDN_LVDS1 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 1
7 PDN_ANA_CH4 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 4
6 PDN_ANA_CH3 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 3
5 PDN_ANA_CH2 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 2
4 PDN_ANA_CH1 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 1
3 INVERT_CH4 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 4(1)
2 INVERT_CH3 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 3(1)
1 INVERT_CH2 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 2(1)
0 INVERT_CH1 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 1(1)
Has no effect on test patterns.

Register 25 (address = 19h)

Figure 135. Register 25
15 14 13 12 11 10 9 8
GAIN_CH5 0 OFFSET_CH5
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH5
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 48. Register 25 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH5 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 5 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH5 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 5 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 26, bits 9-0.

Register 26 (address = 1Ah)

Figure 136. Register 26
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH5
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH5
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 49. Register 26 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH5 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 5 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 25, bits 9-0.

Register 27 (address = 1Bh)

Figure 137. Register 27
15 14 13 12 11 10 9 8
GAIN_CH6 0 OFFSET_CH6
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH6
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 50. Register 27 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH6 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 6 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH6 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 6 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 28, bits 9-0.

Register 28 (address = 1Ch)

Figure 138. Register 28
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH6
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH6
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 51. Register 28 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH6 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 6 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 27, bits 9-0.

Register 29 (address = 1Dh)

Figure 139. Register 29
15 14 13 12 11 10 9 8
GAIN_CH7 0 OFFSET_CH7
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH7
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 52. Register 29 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH7 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 7 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH7 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 7 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 30, bits 9-0.

Register 30 (address = 1Eh)

Figure 140. Register 30
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH7
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH7
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 53. Register 30 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH7 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 7 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 29, bits 9-0.

Register 31 (address = 1Fh)

Figure 141. Register 31
15 14 13 12 11 10 9 8
GAIN_CH8 0 OFFSET_CH8
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH8
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 54. Register 31 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH8 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 8 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH8 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 8 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 32, bits 9-0.

Register 32 (address = 20h)

Figure 142. Register 32
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH8
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 55. Register 32 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH8 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 16 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 31, bits 9-0.

Register 33 (address = 21h)

Figure 143. Register 33
15 14 13 12 11 10 9 8
PAT_PRBS_
LVDS5
PAT_PRBS_
LVDS6
PAT_PRBS_
LVDS7
PAT_PRBS_
LVDS8
PAT_LVDS5[2:0] PAT_
LVDS6[2:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PAT_LVDS6[2:0] 0 HPF_CORNER_CH5-8[3:0] DIG_HPF_EN_CH5-8
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 56. Register 33 Field Descriptions

Bit Field Type Reset Description
15 PAT_PRBS_LVDS5 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 5 can be enabled with this bit; see the Test Patterns section for further details.
14 PAT_PRBS_LVDS6 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 6 can be enabled with this bit; see the Test Patterns section for further details.
13 PAT_PRBS_LVDS7 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 7 can be enabled with this bit; see the Test Patterns section for further details.
12 PAT_PRBS_LVDS8 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 8 can be enabled with this bit; see the Test Patterns section for further details.
11-9 PAT_LVDS5[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 5 can be programmed with these bits; see Table 45 for bit descriptions.
8-6 PAT_LVDS6[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 6 can be programmed with these bits; see Table 45 for bit descriptions.
5 0 R/W 0h Must write 0
4-1 HPF_CORNER_CH5-8[3:0] R/W 0h When the DIG_HPF_EN_CH5-8 bit is set to 1, the digital HPF characteristic for the corresponding channels can be programmed by setting the value of k with these bits. Characteristics of a digital high-pass transfer function applied to the output data for a given value of k is defined by:
AFE5816 q_yn_bas623.gif
Note that the value of k can be from 2 to 10 (0010b to 1010b); see the Digital HPF section for further details.
0 DIG_HPF_EN_CH5-8 R/W 0h 0 = Digital HPF disabled for channels 5 to 8 (default)
1 = Enables digital HPF for channels 5 to 8(1)
Should be set same as DIG_HPF_EN_CH1-4

Register 35 (address = 23h)

Figure 144. Register 35
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PAT_LVDS7[2:0] PAT_LVDS8[2:0] 0 0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 57. Register 35 Field Descriptions

Bit Field Type Reset Description
15-8 0 R/W 0h Must write 0
7-5 PAT_LVDS7[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 7 can be programmed with these bits; see Table 45 for bit descriptions.
4-2 PAT_LVDS8[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 8 can be programmed with these bits; see Table 45 for bit descriptions.
1-0 0 R/W 0h Must write 0

Register 36 (address = 24h)

Figure 145. Register 36
15 14 13 12 11 10 9 8
PDN_DIG_
CH8
PDN_DIG_
CH7
PDN_DIG_
CH6
PDN_DIG_
CH5
PDN_LVDS8 PDN_LVDS7 PDN_LVDS6 PDN_LVDS5
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PDN_ANA_
CH8
PDN_ANA_
CH7
PDN_ANA_
CH6
PDN_ANA_
CH5
INVERT_
CH8
INVERT_
CH7
INVERT_
CH6
INVERT_
CH5
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 58. Register 36 Field Descriptions

Bit Field Type Reset Description
15 PDN_DIG_CH8 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 8
14 PDN_DIG_CH7 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 7
13 PDN_DIG_CH6 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 6
12 PDN_DIG_CH5 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 5
11 PDN_LVDS8 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 8
10 PDN_LVDS7 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 7
9 PDN_LVDS6 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 6
8 PDN_LVDS5 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 5
7 PDN_ANA_CH8 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 8
6 PDN_ANA_CH7 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 7
5 PDN_ANA_CH6 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 6
4 PDN_ANA_CH5 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 5
3 INVERT_CH8 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 8(1)
2 INVERT_CH7 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 7(1)
1 INVERT_CH6 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 6(1)
0 INVERT_CH5 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 5(1)
Has no effect on test patterns.

Register 37 (address = 25h)

Figure 146. Register 37
15 14 13 12 11 10 9 8
GAIN_CH9 0 OFFSET_CH9
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH9
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 59. Register 37 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH9 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 9 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH9 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 9 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 38, bits 9-0.

Register 38 (address = 26h)

Figure 147. Register 38
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH9
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 60. Register 38 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH9 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 9 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 37, bits 9-0.

Register 39 (address = 27h)

Figure 148. Register 39
15 14 13 12 11 10 9 8
GAIN_CH10 0 OFFSET_CH10
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH10
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 61. Register 39 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH10 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 10 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH10 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 10 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 40, bits 9-0.

Register 40 (address = 28h)

Figure 149. Register 40
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH10
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH10
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 62. Register 40 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH10 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 10 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 39, bits 9-0.

Register 41 (address = 29h)

Figure 150. Register 41
15 14 13 12 11 10 9 8
GAIN_CH11 0 OFFSET_CH11
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH11
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 63. Register 41 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH11 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 11 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH11 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 11 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 42, bits 9-0.

Register 42 (address = 2Ah)

Figure 151. Register 42
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH11
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH11
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 64. Register 42 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH11 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 11 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 41, bits 9-0.

Register 43 (address = 2Bh)

Figure 152. Register 43
15 14 13 12 11 10 9 8
GAIN_CH12 0 OFFSET_CH12
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH12
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 65. Register 43 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH12 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 12 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH12 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 12 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 44, bits 9-0.

Register 44 (address = 2Ch)

Figure 153. Register 44
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH12
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH12
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 66. Register 44 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH12 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 12 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 43, bits 9-0.

Register 45 (address = 2Dh)

Figure 154. Register 45
15 14 13 12 11 10 9 8
PAT_PRBS_
LVDS9
PAT_PRBS_
LVDS10
PAT_PRBS_
LVDS11
PAT_PRBS_
LVDS12
PAT_LVDS9[2:0] PAT_
LVDS10[2:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PAT_LVDS10[2:0] HPF_ROUND_EN_CH9-16 HPF_CORNER_CH9-12[3:0] DIG_HPF_EN_CH9-12
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 67. Register 45 Field Descriptions

Bit Field Type Reset Description
15 PAT_PRBS_LVDS9 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 9 can be enabled with this bit; see the Test Patterns section for further details.
14 PAT_PRBS_LVDS10 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 10 can be enabled with this bit; see the Test Patterns section for further details.
13 PAT_PRBS_LVDS11 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 11 can be enabled with this bit; see the Test Patterns section for further details.
12 PAT_PRBS_LVDS12 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 12 can be enabled with this bit; see the Test Patterns section for further details.
11-9 PAT_LVDS9[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 9 can be programmed with these bits; see Table 45 for bit descriptions.
8-6 PAT_LVDS10[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 10 can be programmed with these bits; see Table 45 for bit descriptions.
5 HPF_ROUND_EN_CH9-16 R/W 0h 0 = Rounding in the ADC HPF is disabled for channels 9-16. The HPF output is truncated to be mapped to the ADC resolution bits.
1 = HPF output of channels 9-16 is mapped to the ADC resolution bits by the round-off operation.
4-1 HPF_CORNER_CH9-12[3:0] R/W 0h When the DIG_HPF_EN_CH9-12 bit is set to 1, the digital HPF characteristic for the corresponding channels can be programmed by setting the value of k with these bits. Characteristics of a digital high-pass transfer function applied to the output data for a given value of k is defined by:
AFE5816 q_yn_bas623.gif
Note that the value of k can be from 2 to 10 (0010b to 1010b); see the Digital HPF section for further details.
0 DIG_HPF_EN_CH9-12 R/W 0h 0 = Digital HPF disabled for channels 9 to 12 (default)
1 = Enables digital HPF for channels 9 to 12

Register 47 (address = 2Fh)

Figure 155. Register 47
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PAT_LVDS11[2:0] PAT_LVDS12[2:0] 0 0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 68. Register 47 Field Descriptions

Bit Field Type Reset Description
15-8 0 R/W 0h Must write 0
7-5 PAT_LVDS11[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 11 can be programmed with these bits; see Table 45 for bit descriptions.
4-2 PAT_LVDS12[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 12 can be programmed with these bits; see Table 45 for bit descriptions.
1-0 0 R/W 0h Must write 0

Register 48 (address = 30h)

Figure 156. Register 48
15 14 13 12 11 10 9 8
PDN_DIG_
CH12
PDN_DIG_
CH11
PDN_DIG_
CH10
PDN_DIG_
CH9
PDN_LVDS12 PDN_LVDS11 PDN_LVDS10 PDN_LVDS9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PDN_ANA_
CH12
PDN_ANA_
CH11
PDN_ANA_
CH10
PDN_ANA_
CH9
INVERT_
CH12
INVERT_
CH11
INVERT_
CH10
INVERT_
CH9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 69. Register 48 Field Descriptions

Bit Field Type Reset Description
15 PDN_DIG_CH12 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 12
14 PDN_DIG_CH11 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 11
13 PDN_DIG_CH10 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 10
12 PDN_DIG_CH9 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 9
11 PDN_LVDS12 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 12
10 PDN_LVDS11 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 11
9 PDN_LVDS10 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 10
8 PDN_LVDS9 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 9
7 PDN_ANA_CH12 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 12
6 PDN_ANA_CH11 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 11
5 PDN_ANA_CH10 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 10
4 PDN_ANA_CH9 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 9
3 INVERT_CH12 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 12(1)
2 INVERT_CH11 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 11(1)
1 INVERT_CH10 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 10(1)
0 INVERT_CH9 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 9(1)
Has no effect on test patterns.

Register 49 (address = 31h)

Figure 157. Register 49
15 14 13 12 11 10 9 8
GAIN_CH13 0 OFFSET_CH13
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH13
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 70. Register 49 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH13 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 13 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH13 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 13 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 50, bits 9-0.

Register 50 (address = 32h)

Figure 158. Register 50
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH13
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH13
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 71. Register 50 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH13 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 13 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 49, bits 9-0.

Register 51 (address = 33h)

Figure 159. Register 51
15 14 13 12 11 10 9 8
GAIN_CH14 0 OFFSET_CH14
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH14
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 72. Register 51 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH14 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 14 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH14 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 14 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 52, bits 9-0.

Register 52 (address = 34h)

Figure 160. Register 52
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH14
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH14
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 73. Register 52 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH14 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 14 can be obtained with this 10-bit register. The offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 51, bits 9-0.

Register 53 (address = 35h)

Figure 161. Register 53
15 14 13 12 11 10 9 8
GAIN_CH15 0 OFFSET_CH15
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH15
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 74. Register 53 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH15 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 15 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH15 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 15 can be obtained with this 10-bit register. the offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 54, bits 9-0.

Register 54 (address = 36h)

Figure 162. Register 54
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH15
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH15
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 75. Register 54 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH15 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 15 can be obtained with this 10-bit register. the offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 53, bits 9-0.

Register 55 (address = 37h)

Figure 163. Register 55
15 14 13 12 11 10 9 8
GAIN_CH16 0 OFFSET_CH16
R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH16
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 76. Register 55 Field Descriptions

Bit Field Type Reset Description
15-11 GAIN_CH16 R/W 0h When the DIG_GAIN_EN bit is set to 1, the digital gain value for channel 16 can be obtained with this register. For an N value (decimal equivalent of binary) written to these bits, the digital gain gets set to N × 0.2 dB.
10 0 R/W 0h Must write 0
9-0 OFFSET_CH16 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 16 can be obtained with this 10-bit register. the offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 56, bits 9-0.

Register 56 (address = 38h)

Figure 164. Register 56
15 14 13 12 11 10 9 8
0 0 0 0 0 0 OFFSET_CH16
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
OFFSET_CH16
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 77. Register 56 Field Descriptions

Bit Field Type Reset Description
15-10 0 R/W 0h Must write 0
9-0 OFFSET_CH16 R/W 0h When the DIG_OFFSET_EN bit is set to 1, the offset value for channel 16 can be obtained with this 10-bit register. the offset value is in twos complement format and its LSB corresponds to a 14-bit LSB. Write the same offset value in register 55, bits 9-0.

Register 57 (address = 39h)

Figure 165. Register 57
15 14 13 12 11 10 9 8
PAT_PRBS_
LVDS13
PAT_PRBS_
LVDS14
PAT_PRBS_
LVDS15
PAT_PRBS_
LVDS16
PAT_LVDS13[2:0] PAT_
LVDS14[2:0]
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PAT_LVDS14[2:0] 0 HPF_CORNER_CH13-16[3:0] DIG_HPF_EN_CH13-16
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 78. Register 57 Field Descriptions

Bit Field Type Reset Description
15 PAT_PRBS_LVDS13 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 13 can be enabled with this bit; see the Test Patterns section for further details.
14 PAT_PRBS_LVDS14 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 14 can be enabled with this bit; see the Test Patterns section for further details.
13 PAT_PRBS_LVDS15 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 15 can be enabled with this bit; see the Test Patterns section for further details.
12 PAT_PRBS_LVDS16 R/W 0h When the PAT_SELECT_IND bit is set to 1, the PRBS pattern on LVDS output 16 can be enabled with this bit; see the Test Patterns section for further details.
11-9 PAT_LVDS13[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 13 can be programmed with these bits; see Table 45 for bit descriptions.
8-6 PAT_LVDS14[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 14 can be programmed with these bits; see Table 45 for bit descriptions.
5 0 R/W 0h Must write 0
4-1 HPF_CORNER_CH13-16[3:0] R/W 0h When the DIG_HPF_EN_CH13-16 bit is set to 1, the digital HPF characteristic for the corresponding channels can be programmed by setting the value of k with these bits. Characteristics of a digital high-pass transfer function applied to the output data for a given value of k is defined by:
AFE5816 q_yn_bas623.gif
Note that the value of k can be from 2 to 10 (0010b to 1010b); see the Digital HPF section for further details.
0 DIG_HPF_EN_CH13-16 R/W 0h 0 = Digital HPF disabled for channels 13 to 16 (default)(1)
1 = Enables digital HPF for channels 13 to 16
Should be set same as DIG_HPF_EN_CH9-12

Register 59 (address = 3Bh)

Figure 166. Register 59
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PAT_LVDS15[2:0] PAT_LVDS16[2:0] 0 0
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 79. Register 59 Field Descriptions

Bit Field Type Reset Description
15-8 0 R/W 0h Must write 0
7-5 PAT_LVDS15[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, the different pattern on LVDS output 15 can be programmed with these bits; see Table 45 for bit descriptions.
4-2 PAT_LVDS16[2:0] R/W 0h When the PAT_SELECT_IND bit is set to 1, then the different pattern on LVDS output 16 can be programmed with these bits; see Table 45 for bit descriptions.
1-0 0 R/W 0h Must write 0

Register 60 (address = 3Ch)

Figure 167. Register 60
15 14 13 12 11 10 9 8
PDN_DIG_
CH16
PDN_DIG_
CH15
PDN_DIG_
CH14
PDN_DIG_
CH13
PDN_LVDS16 PDN_LVDS15 PDN_LVDS14 PDN_LVDS13
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PDN_ANA_
CH16
PDN_ANA_
CH15
PDN_ANA_
CH14
PDN_ANA_
CH13
INVERT_
CH16
INVERT_
CH15
INVERT_
CH14
INVERT_
CH13
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 80. Register 60 Field Descriptions

Bit Field Type Reset Description
15 PDN_DIG_CH16 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 16
14 PDN_DIG_CH15 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 15
13 PDN_DIG_CH14 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 14
12 PDN_DIG_CH13 R/W 0h 0 = Normal operation (default)
1 = Powers down the digital block for channel 13
11 PDN_LVDS16 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 16
10 PDN_LVDS15 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 15
9 PDN_LVDS14 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 14
8 PDN_LVDS13 R/W 0h 0 = Normal operation (default)
1 = Powers down LVDS output line 13
7 PDN_ANA_CH16 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 16
6 PDN_ANA_CH15 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 15
5 PDN_ANA_CH14 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 14
4 PDN_ANA_CH13 R/W 0h 0 = Normal operation (default)
1 = Powers down the analog block for channel 13
3 INVERT_CH16 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 16(1)
2 INVERT_CH15 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 15(1)
1 INVERT_CH14 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 14(1)
0 INVERT_CH13 R/W 0h 0 = Normal operation (default)
1 = Inverts digital output data sent on LVDS output line 13(1)
Has no effect on test patterns.

Register 65 (address = 41h)

Figure 168. Register 65
15 14 13 12 11 10 9 8
PLLRST1 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 81. Register 65 Field Descriptions

Bit Field Type Reset Description
15 PLLRST1 R/W 0h Part of initialization sequence.
To initialize PLL1, first set PLLRST1 to '1' and again set PLLRST1 to '0'
14-0 0 R/W 0h Must write 0

Register 66 (address = 42h)

Figure 169. Register 66
15 14 13 12 11 10 9 8
PLLRST2 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 82. Register 66 Field Descriptions

Bit Field Type Reset Description
15 PLLRST2 R/W 0h Part of initialization sequence.
To initialize PLL2, first set PLLRST2 to '1' and again set PLLRST1 to '0'
14-0 0 R/W 0h Must write 0

Register 67 (address = 43h)

Figure 170. Register 67
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 LVDS_DCLK_DELAY_PROG[3:0] 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 83. Register 67 Field Descriptions

Bit Field Type Reset Description
15-5 0 R/W 0h Must write 0
4-1 LVDS_DCLK_DELAY_PROG[3:0] R/W 0h The LVDS DCLK output delay is programmable with 110-ps steps. Delay values are in twos complement format. Increasing the positive delay increases setup time and reduces hold time, and vice-versa for the negative delay.
0000 = No delay
0001 = 110 ps
0010 = 220 ps

1110 = –220 ps
1111 = –110 ps
0 0 R/W 0h Must write 0

VCA Register Map

This section discusses the VCA register map. A register map is available in Table 84.

DTGC_WR_EN must be set to 0 before programming the VCA register map.

Table 84. VCA Register Map

REGISTER ADDRESS REGISTER DATA(1)
DECIMAL HEX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
192 C0 0 0 0 0 0 0 0 0 0 0 0 1X_CLK_
BUF_
MODE
16X_CLK_
BUF_
MODE
CW_CLK_MODE CW_TGC_SEL
193 C1 CW_MIX_PH_CH4 CW_MIX_PH_CH3 CW_MIX_PH_CH2 CW_MIX_PH_CH1
194 C2 CW_MIX_PH_CH8 CW_MIX_PH_CH7 CW_MIX_PH_CH6 CW_MIX_PH_CH5
195 C3 CW_MIX_PH_CH12 CW_MIX_PH_CH11 CW_MIX_PH_CH10 CW_MIX_PH_CH9
196 C4 CW_MIX_PH_CH16 CW_MIX_PH_CH15 CW_MIX_PH_CH14 CW_MIX_PH_CH13
197 C5 PDCH16 PDCH15 PDCH14 PDCH13 PDCH12 PDCH11 PDCH10 PDCH9 PDCH8 PDCH7 PDCH6 PDCH5 PDCH4 PDCH3 PDCH2 PDCH1
198 C6 0 0 0 0 0 0 0 0 0 0 0 0 PDWN_
FILTER
PDWN_
LNA
GBL_
PDWN
FAST_
PDWN
199 C7 0 0 0 0 LNA_HPF_PROG LNA_HPF_DIS LPF_PROG 0 0 0 0 0 0 0
200 C8 0 0 0 LOW_POW 0 0 0 0 0 0 0 0 0 0 0 0
206 CE 0 MEDIUM_
POW
0 0 0 0 0 0 0 0 0 0 0 0 0 0
230 E6 0 0 0 0 0 0 0 0 0 0 0 TR_EXT_
DIS
TR_DIS4 TR_DIS3 TR_DIS2 TR_DIS1
The default value of all registers is 0.

Description of VCA Registers

Register 192 (address = C0h)

Figure 171. Register 192
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 1X_CLK_BUF_MODE 16X_CLK_BUF_MODE CW_CLK_MODE CW_TGC_SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 85. Register 192 Field Descriptions

Bit Field Type Reset Description
15-5 0 R/W 0h Must write 0
4 1X_CLK_BUF_MODE R/W 0h 0 = Accepts CMOS clocks
1 = Accepts differential clocks
3 16X_CLK_BUF_MODE R/W 0h 0 = Accepts differential clocks
1 = Accepts CMOS clocks
2-1 CW_CLK_MODE R/W 0h Programs CW path clock mode
00 = 16X mode
01 = 8X mode
10 = 4X mode
11 = 1X mode
0 CW_TGC_SEL R/W 0h 0 = TGC mode
1 = CW mode
Note: In CW mode, the LNA gain changes to a fixed value of 18 dB and the input attenuator block and low-pass filter are disabled. Thus, TGC and CW mode cannot be used at the same time.

Register 193 (address = C1h)

Figure 172. Register 193
15 14 13 12 11 10 9 8
CW_MIX_PH_CH4 CW_MIX_PH_CH3
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CW_MIX_PH_CH2 CW_MIX_PH_CH1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 86. Register 193 Field Descriptions

Bit Field Type Reset Description
15-12 CW_MIX_PH_CH4 R/W 0h These bits control the CW mixer phase for channel 4.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
11-8 CW_MIX_PH_CH3 R/W 0h These bits control the CW mixer phase for channel 3.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
7-4 CW_MIX_PH_CH2 R/W 0h These bits control the CW mixer phase for channel 2.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
3-0 CW_MIX_PH_CH1 R/W 0h These bits control the CW mixer phase for channel 1.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.

Register 194 (address = C2h)

Figure 173. Register 194
15 14 13 12 11 10 9 8
CW_MIX_PH_CH8 CW_MIX_PH_CH7
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CW_MIX_PH_CH6 CW_MIX_PH_CH5
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 87. Register 194 Field Descriptions

Bit Field Type Reset Description
15-12 CW_MIX_PH_CH8 R/W 0h These bits control the CW mixer phase for channel 8.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
11-8 CW_MIX_PH_CH7 R/W 0h These bits control the CW mixer phase for channel 7.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
7-4 CW_MIX_PH_CH6 R/W 0h These bits control the CW mixer phase for channel 6.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
3-0 CW_MIX_PH_CH5 R/W 0h These bits control the CW mixer phase for channel 5.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.

Register 195 (address = C3h)

Figure 174. Register 195
15 14 13 12 11 10 9 8
CW_MIX_PH_CH12 CW_MIX_PH_CH11
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CW_MIX_PH_CH10 CW_MIX_PH_CH9
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 88. Register 195 Field Descriptions

Bit Field Type Reset Description
15-12 CW_MIX_PH_CH12 R/W 0h These bits control the CW mixer phase for channel 12.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
11-8 CW_MIX_PH_CH11 R/W 0h These bits control the CW mixer phase for channel 11.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
7-4 CW_MIX_PH_CH10 R/W 0h These bits control the CW mixer phase for channel 10.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
3-0 CW_MIX_PH_CH9 R/W 0h These bits control the CW mixer phase for channel 9.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.

Register 196 (address = C4h)

Figure 175. Register 196
15 14 13 12 11 10 9 8
CW_MIX_PH_CH16 CW_MIX_PH_CH15
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CW_MIX_PH_CH14 CW_MIX_PH_CH13
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 89. Register 196 Field Descriptions

Bit Field Type Reset Description
15-12 CW_MIX_PH_CH16 R/W 0h These bits control the CW mixer phase for channel 16.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
11-8 CW_MIX_PH_CH15 R/W 0h These bits control the CW mixer phase for channel 15.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
7-4 CW_MIX_PH_CH14 R/W 0h These bits control the CW mixer phase for channel 14.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.
3-0 CW_MIX_PH_CH13 R/W 0h These bits control the CW mixer phase for channel 13.
Writing N to these bits sets the corresponding channel phase to N × 22.5° (N = 0 to 15); see Table 90 for further details.

Table 90. CW Mixer Phase Delay vs Register Settings

BIT SETTINGS CW_MIX_PH_CHX, CW_MIX_PH_CHY PHASE SHIFT
0000 0
0001 22.5°
0010 45°
0011 67.5°
0100 90°
0101 112.5°
0110 135°
0111 157.5°
1000 180°
1001 202.5°
1010 225°
1011 247.5°
1100 270°
1101 292.5°
1110 315°
1111 337.5°

Register 197 (address = C5h)

Figure 176. Register 197
15 14 13 12 11 10 9 8
PDCH16 PDCH15 PDCH14 PDCH13 PDCH12 PDCH11 PDCH10 PDCH9
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PDCH8 PDCH7 PDCH6 PDCH5 PDCH4 PDCH3 PDCH2 PDCH1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 91. Register 197 Field Descriptions

Bit Field Type Reset Description
15 PDCH16 R/W 0h 0 = Default
1 = Channel 16 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
14 PDCH 15 R/W 0h 0 = Default
1 = Channel 15 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
13 PDCH 14 R/W 0h 0 = Default
1 = Channel 14 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
12 PDCH 13 R/W 0h 0 = Default
1 = Channel 13 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
11 PDCH 12 R/W 0h 0 = Default
1 = Channel 12 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
10 PDCH 11 R/W 0h 0 = Default
1 = Channel 11 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
9 PDCH 10 R/W 0h 0 = Default
1 = Channel 10 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
8 PDCH 9 R/W 0h 0 = Default
1 = Channel 9 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
7 PDCH 8 R/W 0h 0 = Default
1 = Channel 8 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
6 PDCH 7 R/W 0h 0 = Default
1 = Channel 7 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
5 PDCH 6 R/W 0h 0 = Default
1 = Channel 6 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
4 PDCH 5 R/W 0h 0 = Default
1 = Channel 5 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
3 PDCH 4 R/W 0h 0 = Default
1 = Channel 4 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
2 PDCH 3 R/W 0h 0 = Default
1 = Channel 3 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
1 PDCH 2 R/W 0h 0 = Default
1 = Channel 2 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.
0 PDCH 1 R/W 0h 0 = Default
1 = Channel 1 is powered down.
This bit powers down the channel of the VCA die only (LNA, LPF, CW mixer). This bit does not affect the ADC channel.

Register 198 (address = C6h)

Figure 177. Register 198
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 PDWN_FILTER PDWN_LNA GBL_PDWN FAST_PDWN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 92. Register 198 Field Descriptions

Bit Field Type Reset Description
15-4 0 R/W 0h Must write 0
3 PDWN_FILTER R/W 0h 0 = Default
1 = The LPF in the VCA die is powered down
2 PDWN_LNA R/W 0h 0 = Default
1 = The LNA in the VCA is powered down
1 GBL_PDWN R/W 0h 0 = Normal operation
1 = The LNA, LPF, CW mixer, and TGC control engine are completely powered down (slow wake response) for the VCA die.
Note that enabling this bit does not power-down the ADC. This bit only powers down the VCA die.
0 FAST_PDWN R/W 0h 0 = Normal operation
1 = The LNA, LPF, and CW mixer are partially powered down (fast wake response) for the VCA die.
Note that enabling this bit does not power-down the ADC. This bit only powers down the VCA die.

Register 199 (address = C7h)

Figure 178. Register 199
15 14 13 12 11 10 9 8
0 0 0 0 LNA_HPF_PROG LNA_HPF_DIS LPF_PROG
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
LPF_PROG 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 93. Register 199 Field Descriptions

Bit Field Type Reset Description
15-12 0 R/W 0h Must write 0
11-10 LNA_HPF_PROG R/W 0h These bits control the LNA HPF cutoff frequency.
00 = 75 kHz
01 = 150 kHz
10 = 300 kHz
11 = 600 kHz
9 LNA_HPF_DIS R/W 0h 0 = LNA HPF enabled
1 = LNA HPF disabled
8-7 LPF_PROG R/W 0h These bits program the cutoff frequency of the antialiasing LPF.
00 = 15 MHz in low-noise and medium-power mode, 7.5 MHz in low-power mode
01 = 10 MHz in low-noise and medium-power mode, 5 MHz in low-power mode
10 = 25 MHz in low-noise and medium-power mode, 12.5 MHz in low-power mode
11 = 20 MHz in low-noise and medium-power mode, 10 MHz in low-power mode
6-0 0 R/W 0h Must write 0

Register 200 (address = C8h)

Figure 179. Register 200
15 14 13 12 11 10 9 8
0 0 0 LOW_POW 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 94. Register 200 Field Descriptions

Bit Field Type Reset Description
15-13 0 R/W 0h Must write 0
12 LOW_POW R/W 0h 0 = Default
1 = In TGC mode the VCA die is set to low-power mode. No effect in CW mode.
11-0 0 R/W 0h Must write 0

Register 206 (address = CEh)

Figure 180. Register 206
15 14 13 12 11 10 9 8
0 MEDIUM_POW 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 95. Register 206 Field Descriptions

Bit Field Type Reset Description
15 0 R/W 0h Must write 0
14 MEDIUM_POW R/W 0h 0 = Default
1 = In TGC mode, the VCA die is set to medium-power mode. The LOW_POW bit must be set to 0 to enable this mode. This bit has no effect in CW mode.
13-0 0 R/W 0h Must write 0

Register 230 (address = E6h)

Figure 181. Register 230
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
0 0 0 TR_EXT_DIS TR_DIS4 TR_DIS3 TR_DIS2 TR_DIS1
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 96. Register 230 Field Descriptions

Bit Field Type Reset Description
15-5 0 R/W 0h Must write 0
4 TR_EXT_DIS(1) R/W 0h 0 = The TR_EN<x> pins are used to disconnect the LNA HPF from the INP pins
1 = The TR_DIS[4:1] register bits are used to disconnect the LNA HPF from the INP pin
3 TR_DIS4(1) R/W 0h When the TR_EXT_DIS bit is set to 1:
0 = Disconnects the LNA HPF from the input of channels 13, 14, 15, and 16
1 = Enables the LNA HPF at the input of channels 13, 14, 15, and 16
2 TR_DIS3(1) R/W 0h When the TR_EXT_DIS bit is set to 1:
0 = Disconnects the LNA HPF from the input of channels 9, 10, 11, and 12
1 = Enables the LNA HPF at the input of channels 9, 11, 11, and 12
1 TR_DIS2(1) R/W 0h When the TR_EXT_DIS bit set to 1:
0 = Disconnects the LNA HPF from the input of channels 5, 6, 7, and 8
1 = Enables the LNA HPF at the input of channels 5, 6, 7, and 8
0 TR_DIS1(1) R/W 0h When the TR_EXT_DIS bit is set to 1:
0 = Disconnects the LNA HPF from the input of channels 1, 2, 3, and 4
1 = Enables the LNA HPF at the input of channels 1, 2, 3, and 4
Note that when this bit is enabled, the LNA HPF remains powered up and is disconnected only from the input. This feature can be used for better overload recovery by disconnecting the LNA HPF during AFE overload conditions.

DTGC Register Map

This section discusses the DTGC register map. A register map is available in Table 24.

DTGC_WR_EN must be set to 1 before programming other bits of the global register map.

Table 97. DTGC Register Map

REGISTER ADDRESS REGISTER DATA
DECIMAL HEX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 MEM_WORD_0
2-160 2-A0 MEM_WORD_1 to MEM_WORD_159
161 A1 START_GAIN_0 STOP_GAIN_0
162 A2 POS_STEP_0 NEG_STEP_0
163 A3 START_INDEX_0 STOP_INDEX_0
164 A4 START_GAIN_TIME_0
165 A5 HOLD_GAIN_TIME_0
166 A6 START_GAIN_1 STOP_GAIN_1
167 A7 POS_STEP_1 NEG_STEP_1
168 A8 START_INDEX_1 STOP_INDEX_1
169 A9 START_GAIN_TIME_1
170 AA HOLD_GAIN_TIME_1
171 AB START_GAIN_2 STOP_GAIN_2
172 AC POS_STEP_2 NEG_STEP_2
173 AD START_INDEX_2 STOP_INDEX_2
174 AE START_GAIN_TIME_2
175 AF HOLD_GAIN_TIME_2
176 B0 START_GAIN_3 STOP_GAIN_3
177 B1 POS_STEP_3 NEG_STEP_3
178 B2 START_INDEX_3 STOP_INDEX_3
179 B3 START_GAIN_TIME_3
180 B4 HOLD_GAIN_TIME_3
181 B5 SLOPE_
FAC[0]
ENABLE_
INT_
START
MEM_BANK_SEL 0 MANUAL_
START
0 MANUAL_GAIN_DTGC
182 B6 MODE_SEL PROFILE_REG_SEL PROFILE_
EXT_DIS
INP_RES_SEL FLIP_
ATTEN
DIS_
ATTEN
SLOPE_FAC[3:1] 0 0
183 B7 NEXT_CYCLE_WAIT_TIME
185 B9 FIX_
ATTEN_
EN_0
ATTENUATION_0 FIX_
ATTEN_
EN_1
ATTENUATION_1
186 BA FIX_
ATTEN_
EN_2
ATTENUATION_2 FIX_
ATTEN_
EN_3
ATTENUATION_3

Description of DTGC Register

DTGC Registers

DTGC_WR_EN must be set to 1 to write these registers.

Register 1 (address = 1h)

Figure 182. Register 1
15 14 13 12 11 10 9 8
MEM_WORD_0
R/W-Undefined
7 6 5 4 3 2 1 0
MEM_WORD_0
R/W-Undefined
LEGEND: R/W = Read/Write; -n = value after reset

Table 98. Register 1 Field Descriptions

Bit Field Type Reset Description
15-0 MEM_WORD_0 R/W Undefined The memory word register 0 stores the gain step information that is used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details. A reset operation does not reset this register. After power-up, this register must be explicitly written to its desired content.

Registers 2-160 (address = 2h-A0h)

Figure 183. Registers 2-160
15 14 13 12 11 10 9 8
MEM_WORD_1 to MEM_WORD_159
R/W-Undefined
7 6 5 4 3 2 1 0
MEM_WORD_1 to MEM_WORD_159
R/W-Undefined
LEGEND: R/W = Read/Write; -n = value after reset

Table 99. Registers 2-160 Field Descriptions

Bit Field Type Reset Description
15-0 MEM_WORD_1 to MEM_WORD_159 R/W Undefined The memory word registers from 1 to 159 store the gain step information that is used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details. A reset operation does not reset this register. After power-up, this register must be explicitly written to its desired content.

Register 161 (address = A1h)

Figure 184. Register 161
15 14 13 12 11 10 9 8
START_GAIN_0
R/W-0h
7 6 5 4 3 2 1 0
STOP_GAIN_0
R/W-9Fh
LEGEND: R/W = Read/Write; -n = value after reset

Table 100. Register 161 Field Descriptions

Bit Field Type Reset Description
15-8 START_GAIN_0 R/W 0h These bits determine the start gain value for profile 0 that is used in different DTGC modes; see the Digital TGC Modes section for more details.
7-0 STOP_GAIN_0 R/W 9Fh These bits determine the stop gain value for profile 0 that is used in different DTGC modes; see the Digital TGC Modes section for more details.

Register 162 (address = A2h)

Figure 185. Register 162
15 14 13 12 11 10 9 8
POS_STEP_0
R/W-0h
7 6 5 4 3 2 1 0
NEG_STEP_0
R/W-FFh
LEGEND: R/W = Read/Write; -n = value after reset

Table 101. Register 162 Field Descriptions

Bit Field Type Reset Description
15-8 POS_STEP_0 R/W 0h These bits determine the positive step value for profile 0 that is used in different DTGC modes; see the Digital TGC Modes section for more details.
7-0 NEG_STEP_0 R/W FFh These bits determine the negative step value for profile 0 that is used in different DTGC modes; see the Digital TGC Modes section for more details.

Register 163 (address = A3h)

Figure 186. Register 163
15 14 13 12 11 10 9 8
START_INDEX _0
R/W-0h
7 6 5 4 3 2 1 0
STOP_INDEX _0
R/W-9Fh
LEGEND: R/W = Read/Write; -n = value after reset

Table 102. Register 163 Field Descriptions

Bit Field Type Reset Description
15-8 START_INDEX _0 R/W 0h These bits determine the start index value for profile 0, which is used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.
7-0 STOP_INDEX _0 R/W 9Fh These bits determine the stop index value for profile 0, which is used internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 164 (address = A4h)

Figure 187. Register 164
15 14 13 12 11 10 9 8
START_GAIN_TIME_0
R/W-0h
7 6 5 4 3 2 1 0
START_GAIN_TIME_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 103. Register 164 Field Descriptions

Bit Field Type Reset Description
15-0 START_GAIN_TIME_0 R/W 0h These bits define the start gain time for profile 0 and are used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 165 (address = A5h)

Figure 188. Register 165
15 14 13 12 11 10 9 8
HOLD_GAIN_TIME_0
R/W-0h
7 6 5 4 3 2 1 0
HOLD_GAIN_TIME_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 104. Register 165 Field Descriptions

Bit Field Type Reset Description
15-0 HOLD_GAIN_TIME_0 R/W 0h These bits define the hold gain time for profile 0 and are used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 166 (address = A6h)

Figure 189. Register 166
15 14 13 12 11 10 9 8
START_GAIN_1
R/W-0h
7 6 5 4 3 2 1 0
STOP_GAIN_1
R/W-9Fh
LEGEND: R/W = Read/Write; -n = value after reset

Table 105. Register 166 Field Descriptions

Bit Field Type Reset Description
15-8 START_GAIN_1 R/W 0h These bits determine the start gain value for profile 1 that is used in different DTGC modes; see the Digital TGC Modes section for more details.
7-0 STOP_GAIN_1 R/W 9Fh These bits determine the stop gain value for profile 1 that is used in different DTGC modes; see the Digital TGC Modes section for more details.

Register 167 (address = A7h)

Figure 190. Register 167
15 14 13 12 11 10 9 8
POS_STEP_1
R/W-0h
7 6 5 4 3 2 1 0
NEG_STEP_1
R/W-FFh
LEGEND: R/W = Read/Write; -n = value after reset

Table 106. Register 167 Field Descriptions

Bit Field Type Reset Description
15-8 POS_STEP_1 R/W 0h These bits determine the positive step value for profile 1 that is used in different DTGC modes; see the Digital TGC Modes section for more details.
7-0 NEG_STEP_1 R/W FFh These bits determine the negative step value for profile 1 that is used in different DTGC modes; see the Digital TGC Modes section for more details.

Register 168 (address = A8h)

Figure 191. Register 168
15 14 13 12 11 10 9 8
START_INDEX _1
R/W-0h
7 6 5 4 3 2 1 0
STOP_INDEX _1
R/W-9Fh
LEGEND: R/W = Read/Write; -n = value after reset

Table 107. Register 168 Field Descriptions

Bit Field Type Reset Description
15-8 START_INDEX _1 R/W 0h These bits determine the start index value for profile 1 that is used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.
7-0 STOP_INDEX _1 R/W 9Fh These bits determine the stop index value for profile 1 that is used internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 169 (address = A9h)

Figure 192. Register 169
15 14 13 12 11 10 9 8
START_GAIN_TIME_1
R/W-0h
7 6 5 4 3 2 1 0
START_GAIN_TIME_1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 108. Register 169 Field Descriptions

Bit Field Type Reset Description
15-0 START_GAIN_TIME_1 R/W 0h These bits define the start gain time for profile 1 and are used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 170 (address = AAh)

Figure 193. Register 170
15 14 13 12 11 10 9 8
HOLD_GAIN_TIME_1
R/W-0h
7 6 5 4 3 2 1 0
HOLD_GAIN_TIME_1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 109. Register 170 Field Descriptions

Bit Field Type Reset Description
15-0 HOLD_GAIN_TIME_1 R/W 0h These bits define the hold gain time for profile 1 and are used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 171 (address = ABh)

Figure 194. Register 171
15 14 13 12 11 10 9 8
START_GAIN_2
R/W-0h
7 6 5 4 3 2 1 0
STOP_GAIN_2
R/W-9Fh
LEGEND: R/W = Read/Write; -n = value after reset

Table 110. Register 171 Field Descriptions

Bit Field Type Reset Description
15-8 START_GAIN_2 R/W 0h These bits determine the start gain value for profile 2 that is used in different DTGC modes; see the Digital TGC Modes section for more details.
7-0 STOP_GAIN_2 R/W 9Fh These bits determine the stop gain value for profile 2 that is used in different DTGC modes; see the Digital TGC Modes section for more details.

Register 172 (address = ACh)

Figure 195. Register 172
15 14 13 12 11 10 9 8
POS_STEP_2
R/W-0h
7 6 5 4 3 2 1 0
NEG_STEP_2
R/W-FFh
LEGEND: R/W = Read/Write; -n = value after reset

Table 111. Register 172 Field Descriptions

Bit Field Type Reset Description
15-8 POS_STEP_2 R/W 0h These bits determine the positive step value for profile 2 that is used in different DTGC modes; see the Digital TGC Modes section for more details.
7-0 NEG_STEP_2 R/W FFh These bits determine the negative step value for profile 2 that is used in different DTGC modes; see the Digital TGC Modes section for more details.

Register 173 (address = ADh)

Figure 196. Register 173
15 14 13 12 11 10 9 8
START_INDEX _2
R/W-0h
7 6 5 4 3 2 1 0
STOP_INDEX _2
R/W-9Fh
LEGEND: R/W = Read/Write; -n = value after reset

Table 112. Register 173 Field Descriptions

Bit Field Type Reset Description
15-8 START_INDEX _2 R/W 0h These bits determine the start index value for profile 2 that is used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.
7-0 STOP_INDEX _2 R/W 9Fh These bits determine the stop index value for profile 2 that is used internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 174 (address = AEh)

Figure 197. Register 174
15 14 13 12 11 10 9 8
START_GAIN_TIME_2
R/W-0h
7 6 5 4 3 2 1 0
START_GAIN_TIME_2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 113. Register 174 Field Descriptions

Bit Field Type Reset Description
15-0 START_GAIN_TIME_2 R/W 0h These bits define start gain time for profile 2 and are used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 175 (address = AFh)

Figure 198. Register 175
15 14 13 12 11 10 9 8
HOLD_GAIN_TIME_2
R/W-0h
7 6 5 4 3 2 1 0
HOLD_GAIN_TIME_2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 114. Register 175 Field Descriptions

Bit Field Type Reset Description
15-0 HOLD_GAIN_TIME_2 R/W 0h These bits define hold gain time for profile 2 and are used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 176 (address = B0h)

Figure 199. Register 176
15 14 13 12 11 10 9 8
START_GAIN_3
R/W-0h
7 6 5 4 3 2 1 0
STOP_GAIN_3
R/W-9Fh
LEGEND: R/W = Read/Write; -n = value after reset

Table 115. Register 176 Field Descriptions

Bit Field Type Reset Description
15-8 START_GAIN_3 R/W 0h These bits determine the start gain value for profile 3 that is used in different DTGC modes; see the Digital TGC Modes section for more details.
7-0 STOP_GAIN_3 R/W 9Fh These bits determine the stop gain value for profile 3 that is used in different DTGC modes; see the Digital TGC Modes section for more details.

Register 177 (address = B1h)

Figure 200. Register 177
15 14 13 12 11 10 9 8
POS_STEP_3
R/W-0h
7 6 5 4 3 2 1 0
NEG_STEP_3
R/W-FFh
LEGEND: R/W = Read/Write; -n = value after reset

Table 116. Register 177 Field Descriptions

Bit Field Type Reset Description
15-8 POS_STEP_3 R/W 0h These bits determine the positive step value for profile 3 that is used in different DTGC modes; see the Digital TGC Modes section for more details.
7-0 NEG_STEP_3 R/W FFh These bits determine the negative step value for profile 3 that is used in different DTGC modes; see the Digital TGC Modes section for more details.

Register 178 (address = B2h)

Figure 201. Register 178
15 14 13 12 11 10 9 8
START_INDEX _3
R/W-0h
7 6 5 4 3 2 1 0
NEG_STEP_0
R/W-9Fh
LEGEND: R/W = Read/Write; -n = value after reset

Table 117. Register 178 Field Descriptions

Bit Field Type Reset Description
15-8 START_INDEX _3 R/W 0h These bits determine the start index value for profile 3 that is used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.
7-0 STOP_INDEX _3 R/W 9Fh These bits determine the stop index value for profile 3 that is used internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 179 (address = B3h)

Figure 202. Register 179
15 14 13 12 11 10 9 8
START_GAIN_TIME_3
R/W-0h
7 6 5 4 3 2 1 0
START_GAIN_TIME_3
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 118. Register 179 Field Descriptions

Bit Field Type Reset Description
15-0 START_GAIN_TIME_3 R/W 0h These bits define the start gain time for profile 3 and are used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 180 (address = B4h)

Figure 203. Register 180
15 14 13 12 11 10 9 8
HOLD_GAIN_TIME_3
R/W-0h
7 6 5 4 3 2 1 0
HOLD_GAIN_TIME_3
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 119. Register 180 Field Descriptions

Bit Field Type Reset Description
15-0 HOLD_GAIN_TIME_3 R/W 0h These bits define the hold gain time for profile 3 and are used in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.

Register 181 (address = B5h)

Figure 204. Register 181
15 14 13 12 11 10 9 8
SLOPE_FAC[0] ENABLE_INT_
START
MEM_BANK_SEL 0 MANUAL_
START
0 MANUAL_GAIN_
DTGC
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
MANUAL_GAIN_DTGC
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 120. Register 181 Field Descriptions

Bit Field Type Reset Description
15 SLOPE_FAC[0] R/W 0h This bit is used to control the TGC gain curve slope in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.
14 ENABLE_INT_START R/W 0h 0 = External TGC start signal
1 = Periodic TGC start signal is generated by the device itself; see the Digital TGC Test Modes section for more details.
13-12 MEM_BANK_SEL R/W 0h These bits select the memory bank; see the Internal Non-Uniform Mode section for more details.
11, 9 0 R/W 0h Must write 0
10 MANUAL_START R/W 0h 0 = No operation
1 = The TGC start signal is generated internally for single-shot operation only; see the Digital TGC Test Modes section for more details.
8-0 MANUAL_GAIN_DTGC R/W 0h The value of the gain code is determined with this register in programmable fixed-gain mode; see the Programmable Fixed Gain Mode section for more details.

Register 182 (address = B6h)

Figure 205. Register 182
15 14 13 12 11 10 9 8
MODE_SEL PROFILE_REG_SEL PROFILE_EXT_DIS INP_RES_SEL
R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INP_RES_SEL FLIP_ATTEN DIS_ATTEN SLOPE_FAC[3:1] 0 0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 121. Register 182 Field Descriptions

Bit Field Type Reset Description
15-14 MODE_SEL R/W 0h These bits determine the DTGC mode.
00 = External non-uniform mode
01 = Up, down ramp mode
10 = Programmable fixed-gain mode
11 = Internal non-uniform mode
13-12 PROFILE_REG_SEL R/W 0h These bits determine which profile register to use when the PROFILE_EXT_DIS bit is 1.
00 = Profile 0
01 = Profile 1
10 = Profile 2
01 = Profile 3
11 PROFILE_EXT_DIS R/W 0h 0 = Device pins TGC_PROF<2> and TGC_PROF<1> determine which profile to use
1 = The PROFILE_REG_SEL register bits determine which profile to use
10-7 INP_RES_SEL R/W 0h Depending upon source resistance, proper input attenuation resistance must be selected to obtain 8-dB attenuation. Table 122 lists the values to be written for different source resistances.
6 FLIP_ATTEN R/W 0h 0 = In the TGC gain curve, the attenuation of the attenuator block varies first, followed by the LNA gain variation
1 = In the TGC gain curve, the LNA gain varies first, followed by the attenuation of the attenuator block
5 DIS_ATTEN R/W 0h 0 = Attenuator is enabled
1 = Attenuator is disabled
4-2 SLOPE_FAC[3:1] R/W 0h These bits are used to control the TGC gain curve slope in internal non-uniform mode; see the Internal Non-Uniform Mode section for more details.
1-0 0 R/W 0h Must write 0

Table 122. INP_RES_SEL Values

BIT SETTING SOURCE RESISTANCE
0000 50 Ω
0001 115 Ω
0010 70 Ω
0011 270 Ω
0100 60 Ω
0101 160 Ω
0110 90 Ω
0111 800 Ω
1000 60 Ω
1001 130 Ω
1010 80 Ω
1011 400 Ω
1100 65 Ω
1101 200 Ω
1110 100 Ω
1111 Open

Register 183 (address = B7h)

Figure 206. Register 183
15 14 13 12 11 10 9 8
NEXT_CYCLE_WAIT_TIME
R/W-0h
7 6 5 4 3 2 1 0
NEXT_CYCLE_WAIT_TIME
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 123. Register 183 Field Descriptions

Bit Field Type Reset Description
15-0 NEXT_CYCLE_WAIT_TIME R/W 0h When ENABLE_INT_START is set to 1, the periodicity of the internal start signal is controlled with this register; see the Digital TGC Test Modes section for more details.

Register 185 (address = B9h)

Figure 207. Register 185
15 14 13 12 11 10 9 8
FIX_ATTEN_EN_0 ATTENUATION_0
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
FIX_ATTEN_EN_1 ATTENUATION_1
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 124. Register 185 Field Descriptions

Bit Field Type Reset Description
15 FIX_ATTEN_EN_0 R/W 0h 0 = Default
1 = Enable fixed attenuation mode for profile 0
14-8 ATTENUATION_0 R/W 0h When the FIX_ATTEN_EN_0 bit is set to 1, the attenuation level of the attenuator block is set by the ATTENUATION_0 bits for profile 0. A value of N written in the ATTENUATION_0 register sets the attenuation level at –8 + N × 0.125 dB.
7 FIX_ATTEN_EN_1 R/W 0h 0 = Default
1 = Enable fixed attenuation mode for profile 1
6-0 ATTENUATION_1 R/W 0h When the FIX_ATTEN_EN_1 bit is set to 1, the attenuation level of the attenuator block is set by the ATTENUATION_1 bits for profile 1. A value of N written in the ATTENUATION_1 register sets the attenuation level at –8 + N × 0.125 dB.

Register 186 (address = BAh)

Figure 208. Register 186
15 14 13 12 11 10 9 8
FIX_ATTEN_EN_2 ATTENUATION_2
R/W-0h R/W-0h
7 6 5 4 3 2 1 0
FIX_ATTEN_EN_3 ATTENUATION_3
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset

Table 125. Register 186 Field Descriptions

Bit Field Type Reset Description
15 FIX_ATTEN_EN_2 R/W 0h 0 = Default
1 = Enable fixed attenuation mode for profile 2
14-8 ATTENUATION_2 R/W 0h When the FIX_ATTEN_EN_2 bit is set to 1, the attenuation level of the attenuator block is set by the ATTENUATION_2 bits for profile 2. A value of N written in the ATTENUATION_2 register sets the attenuation level at –8 + N × 0.125 dB.
7 FIX_ATTEN_EN_3 R/W 0h 0 = Default
1 = Enable fixed attenuation mode for profile 3
6-0 ATTENUATION_3 R/W 0h When the FIX_ATTEN_EN_3 bit is set to 1, the attenuation level of the attenuator block is set by the ATTENUATION_3 bits for profile 3. A value of N written in the ATTENUATION_3 register sets the attenuation level at –8 + N × 0.125 dB.