AFE5816 datasheet

SBAS688E April 2015 – September 2017 AFE5816

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

ZAV|289
- MPBG777

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted⁽¹⁾

		MIN	MAX	UNIT
Supply voltage range	AVDD_1P8	–0.3	2.2	V
	AVDD_1P9	–0.3	2.2
	AVDD_3P15	–0.3	3.9
	DVDD_1P2	–0.3	1.35
	DVDD_1P8	–0.3	2.2
Voltage at analog inputs		–0.3	Minimum [2.2, (AVDD_1P9 + 0.3)]	V
Voltage at digital inputs		–0.3	Minimum [2.2, (AVDD_1P9 + 0.3), (DVDD_1P8 + 0.3)]	V
Temperature	Maximum junction temperature (T_J), any condition		105	°C
Temperature	Storage, T_stg	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

8.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±250	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

8.3 Recommended Operating Conditions

over operating free-air temperature range, unless otherwise noted

PARAMETER				MIN	TYP	MAX	UNIT
SUPPLIES
V_{A_1P8}	AVDD_1P8 voltage			1.7	1.8	1.9	V
V_{A_1P9}	AVDD_1P9 voltage	Low-noise mode, medium-power mode		1.8	1.9	2.0	V
V_{A_1P9}	AVDD_1P9 voltage	Low-power mode		1.75	1.8	2.0	V
V_{A_3P15}	AVDD_3P15 voltage			3	3.15	3.3	V
V_{D_1P2}	DVDD_1P2 voltage			1.15	1.2	1.25	V
V_{D_1P8}	DVDD_1P8 voltage			1.7	1.8	1.9	V
TEMPERATURE
T_A	Ambient temperature			–40		85	°C
BIAS VOLTAGES
	Common-mode voltage⁽¹⁾	ADC_CLKP, ADC_CLKM in differential mode			0.7		V
		CLKP_1X, CLKM_1X, CLKP_16X, CLKM_16X in differential mode			1.5
		CW_IP_OUTP, CW_IP_OUTM, CW_QP_OUTP, CW_QP_OUTM			0.9
		(INM1, INP1), (INM2, INP2)…(INM16, INP16)			1
	Bias voltage⁽¹⁾	BAND_GAP			1.2		V
		BIAS_2P5			2.5
		LNA_INCM			1
		SRC_BIAS			0.5
ADC CLOCK INPUT: ADC_CLK
f_CLKIN	ADC clock frequency	14-bit ADC resolution		5		65	MHz
f_CLKIN	ADC clock frequency	12-bit ADC resolution		5		80	MHz
V_DEADC	Differential clock amplitude	Sine-wave, ac-coupled		0.7			V_PP
		LVPECL, ac-coupled			1.6
		LVDS, ac-coupled			0.7
V_SEADC	Single-ended clock amplitude	LVCMOS on ADC_CLKP with ADC_CLKM grounded			1.8		V
D_ADC	ADC_CLK duty cycle			40%	50%	60%
CW CLOCK INPUT: CW_CLK1X, CW_CLK_NX
CW_CLK	CW clock frequency	CW_CLK1X across CW clock modes in relation to CW_CLK1X; see the CW_CLK_MODE register bits in register 192				8	MHz
		CW_CLK_NX across CW clock modes; see the CW_CLK_MODE register bits in register 192	16X mode		16X		CW_ CLK1X
			8X mode		8X
			4X mode		4X
V_DECW	Differential clock amplitude	CW_CLK1X, CW_CLK_NX. LVDS, ac-coupled			0.7		V_PP
V_SECW	Single-ended clock amplitude	LVCMOS on CLKP_1X, CLKP_16X with CLKM_1X, CLKM_16X grounded or floating			3.15		V
D_CW	CLK duty cycle	CW_CLK1X, CW_CLK_NX		40%	50%	60%
DIGITAL OUTPUT (LVDS)
R_L	Differential load resistance				100		Ω

(1) Internally set by the device.

8.4 Thermal Information

THERMAL METRIC⁽¹⁾		AFE5816	UNIT
		ZAV (NFBGA)
		289 PINS
R_θJA	Junction-to-ambient thermal resistance	26.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	5.6	°C/W
R_θJB	Junction-to-board thermal resistance	11.7	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	11.0	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

8.5 Electrical Characteristics: TGC Mode

At T_A = 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, and DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V. Input to the device: input signal is ac-coupled to INP with a 10-nF capacitor and is applied with source resistance R_S = 50 Ω at frequency f_IN = 5 MHz, and a 50-MHz differential clock is applied on ADC_CLK. Device settings: gain code = 319 (total gain = 45 dB), 14-bit ADC resolution, LVDS interface to capture ADC data, and output amplitude V_OUT = –1 dBFS. Minimum and maximum values are specified across the full temperature range.

PARAMETER		TEST CONDITION		MIN	TYP	MAX	UNIT
GENERAL
V_MAX	Maximum linear input voltage	At INP_SOURCE node; see the Functional Block Diagram section			1		V_PP
V_MAX	Maximum linear input voltage	At INPx node; see the Functional Block Diagram section			0.4		V_PP
C_INP	Input capacitance				35		pF
G_CODE	Gain code⁽¹⁾	Programs the total gain		0		319
G_TOT	Total gain	Low-noise mode and medium-power mode		(6 + 0.125 × G_CODE)			dB
G_TOT	Total gain	Low-power mode		(12 + 0.125 × G_CODE)			dB
G_RANGE	Gain range				39		dB
G_SLOPE	Gain slope				0.125		dB/G_CODE
T_TGC	TGC response time	G_CODE changed from 64 to 319			10		µs
V_N,IRN	Input voltage noise	R_S = 0 Ω, calculated in band of 4-MHz to 6-MHz frequency	Low-noise mode		1		nV/√Hz
			Medium-power mode		1.3
			Low-power mode		1.45
I_N,IRN	Input-referred current noise	Across low-noise, medium-power, and low-power mode			1.2		pA/√Hz
NF	Noise figure⁽³⁾	R_S = 50 Ω	Low-noise mode		3.6		dB
			Medium-power mode		4.5
			Low-power mode		5.0
		R_S = 400 Ω	Low-noise mode		1.2		dB
			Medium-power mode		1.5
			Low-power mode		1.6
GENERAL (continued)
K_CORR	Channel-to-channel noise correlation factor⁽²⁾	Without a signal, calculated in a 1-MHz to 10-MHz bandwidth	R_S = 330 Ω		–20		dB
		Without a signal, calculated in a 1-MHz to 10-MHz bandwidth	R_S = 100 Ω		–26
		With a signal, calculated in a 1-MHz to 10-MHz bandwidth	Total gain = 45 dB		–17
		With a signal, calculated in a 1-MHz to 10-MHz bandwidth	Total gain = 26 dB		–14
		With a signal, calculated in a 1-MHz bandwidth around a 5-MHz input signal frequency	Total gain = 45 dB		–13
			Total gain = 26 dB		–10
SNR	Signal-to-noise ratio	SNR calculated in 750 kHz to Nyquist bandwidth	Total gain = 14 dB	65	68		dBFS
SNR	Signal-to-noise ratio	SNR calculated in 750 kHz to Nyquist bandwidth	Total gain = 45 dB	55	58		dBFS
SNR_NB	Narrow-band SNR	SNR calculated in 2-MHz bandwidth around input signal frequency	Total gain = 30 dB	72.5	76		dBFS
LPF	3rd-order, low-pass filter	–3-dB cutoff frequency across LPF_PROG register settings; see register 199	Low-noise and medium-power mode		10		MHz
					15
					20
					25
			Low-power mode		5
					7.5
					10
					12.5
Δ_LPF	LPF bandwidth variation				±5%
Δ_Gr	Channel-to-channel group delay matching	2-MHz to 15-MHz input signal frequency			2		ns
Δ_φ	Channel-to-channel phase matching	15-MHz signal			11		Degrees
G_MATCH	Gain matching	Device-to-device, average across channels	G_CODE < 64		±0.5		dB
		Device-to-device, average across channels	G_CODE > 64	–1	±0.5	1
		Channel-to-channel, same device	G_CODE < 64		±0.5
		Channel-to-channel, same device	G_CODE > 64	–1	±0.5	1
HD2	Second-order harmonic distortion	Output amplitude = –1 dBFS, gain = 45 dB			–65		dBc
HD2	Second-order harmonic distortion	Output amplitude = –1 dBFS, gain = 6 dB			–55		dBc
HD3	Third-order harmonic distortion	Output amplitude = –1 dBFS, gain = 45 dB			–60		dBc
HD3	Third-order harmonic distortion	Output amplitude = –1 dBFS, gain = 6 dB			–60		dBc
THD	Total harmonic distortion	Output amplitude = –1 dBFS, gain = 45 dB			–58		dBc
THD	Total harmonic distortion	Output amplitude = –1 dBFS, gain = 6 dB			–54		dBc
IMD3	Third-order intermodulation distortion	Input frequency 1 = 5 MHz at –1 dBFS, input frequency 2 = 5.01 MHz at –21 dBFS			–75		dBc
XTALK	Fundamental crosstalk	Signal applied to a single channel. Crosstalk measured on neighboring channel.			–55		dBc
PN_1kHz	Phase noise	Calculated at 1-kHz offset from 5-MHz input signal frequency			–129		dBc/Hz
V_ORO	Output offset				±600		LSB
G_LNA	LNA gain range in TGC mode			14 to 45			dB
GENERAL (continued)
HPF_TGC	LNA High-pass filter	–1-dB cutoff frequency across LNA_HPF_PROG register settings; see register 199			75		kHz
					150
					300
					600
ADC SPECIFICATIONS
f_S	Sample rate	14-bit resolution		5		65	MSPS
f_S	Sample rate	12-bit resolution		5		80	MSPS
SNR	Signal-to-noise ratio	14-bit resolution	Without a signal		75		dBFS
		14-bit resolution	With a –1-dBFS signal amplitude		72.5
		12-bit resolution	Without a signal		72
		12-bit resolution	With a –1-dBFS signal amplitude		69.5
V_MAX,ADC	ADC input full-scale range				2		V_PP
POWER DISSIPATION
P_TGC/Ch	Power dissipation per channel: 12-bit ADC resolution and 80-MSPS ADC clock	TGC low-noise mode, 500-mV_PP input signal up to 1% duty cycle applied to 16 channels			94		mW/Ch
		TGC medium-power mode, 500-mV_PP input signal up to 1% duty cycle applied to 16 channels			72
		TGC low-power mode, 500-mV_PP input signal up to 1% duty cycle applied to 16 channels			62
I_{A_1P9}	AVDD_1P9 current (1.9 V)⁽⁴⁾	TGC low-noise mode, 500-mV_PP input signal up to 1% duty cycle applied to 16 channels			430		mA
		TGC medium-power mode, 500-mV_PP input signal up to 1% duty cycle applied to 16 channels			240
		TGC low-power mode, 500-mV_PP input signal up to 1% duty cycle applied to 16 channels			160
I_{A_3P15}	AVDD_3P15 current⁽⁴⁾	TGC low-noise, medium-power, and low-power modes, 500-mV_PP input signal up to 1% duty cycle applied to 16 channels			20		mA
I_{A_1P8}	AVDD_1P8 current⁽⁴⁾	For a 12-bit ADC resolution and an 80-MSPS system clock			170		mA
I_{D_1P2}	DVDD_1P2 current⁽⁴⁾	For a 12-bit ADC resolution and an 80-MSPS system clock			110		mA
I_{A_1P8}	DVDD_1P8 current⁽⁴⁾	For a 12-bit ADC resolution and an 80-MSPS system clock			100		mA
AC PERFORMANCE (Power)
PSRR_{1 kHz}	AC power-supply rejection ratio: tone at output relative to tone on supply	100 mV_PP, 1-kHz tone on supply	AVDD_1P9		–65		dBc
			AVDD_3P15		–90
			AVDD_1P8, DVDD_1P8, and DVDD_1P2		–70
PSMR_{1 kHz}	AC power-supply modulation ratio: intermodulation tone at output resulting from tones at supply and input measured relative to input tone	100 mV_PP, 1-kHz tone on supply and –1-dBFS, 5-MHz tone at input	AVDD_1P9		–45		dBc
			AVDD_3P15		–45
			AVDD_1P8, DVDD_1P8, and DVDD_1P2		–80
POWER DOWN
P_DOWN	Power dissipation in power-down mode	Partial power-down when PDN_FAST = high			17		mW/Ch
P_DOWN	Power dissipation in power-down mode	Complete power-down when PDN_GBL = high			3		mW/Ch
t_UP	Power-up time	Partial power-down when PDN_FAST = high and the device is in partial power-down time for < 500 µs			3		µs
t_UP	Power-up time	Complete power-down when PDN_GBL = high			1		ms

(1) The gain code range from 0 to 63 controls the input attenuation and the gain code range from 64 to 319 controls the LNA gain.

(2) The noise-correlation factor is defined as 10 × log₁₀[Nc / (Nc + Nu)], where Nc is the correlated noise power in a single channel and Nu is the uncorrelated noise power in a single channel. The noise-correlation factor measurement is described by the equation: AFE5816 noise_corelation_eq.gif

where N_16CH is the noise power of the summed 16 channels and N_1CH is the noise power of one channel.

(3) NF is measured as the SNR at the output of the device relative to the SNR at the input resulting from ths noise of source resistance R_S.

(4) Designing the power supply with 2X of the typical current capacity is recommended to take care of current variation across devices, switching current, signal current, and so forth.

8.6 Electrical Characteristics: CW Mode

At T_A = 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, and DVDD_1P8 = 1.8 V. Input to the device: input signal is ac-coupled to INP with a 10-nF capacitor and is applied with source resistance R_S = 50 Ω at frequency f_IN = 2 MHz, CW_CLK1X = 2-MHz differential clock, and CW_CLK_NX = 32-MHz differential clock. Device settings: CW clock mode = 16X, and 1X and 16X clock buffer in differential mode and ADC in power-down mode. Minimum and maximum values are specified across the full temperature range.

PARAMETER		TEST CONDITIONS		TYP	UNIT
GENERAL
V_{MAX, CW}	Maximum input swing			300	mV_PP
R_V2I	Voltage-to-current resistor at LNA output			500	Ω
I_OPP	Peak-to-peak output current per channel			4.8	mA/Ch
V_N,IRCW	Input voltage noise	1 channel		1.55	nV/√Hz
V_N,IRCW	Input voltage noise	16 channels		0.45	nV/√Hz
I_N,ORCW	Output current noise	1 channel		19	pA/√Hz
I_N,ORCW	Output current noise	16 channels		80	pA/√Hz
NF_CW	Noise figure⁽¹⁾	R_S = 100 Ω, 1 channel		4	dB
NF_CW	Noise figure⁽¹⁾	R_S = 100 Ω, 16 channels		4.8	dB
L_CWM	CW mixer conversion loss			4	dB
PN_{1 kHz,CW}	Phase noise	16X CW clock mode, calculated at 1-kHz frequency	Signal to 1 channel	–151	dBc/Hz
PN_{1 kHz,CW}	Phase noise	16X CW clock mode, calculated at 1-kHz frequency	Signal to 16 channels	–161	dBc/Hz
IMD3	Two-tone, third-order intermodulation distortion	f_IN1 = 5 MHz, f_IN2 = 5.01 MHz, both tones at –6-dBFS amplitude, input to all the 16 channels.		–60	dBc
IMD3	Two-tone, third-order intermodulation distortion	f_IN1 = 5 MHz, f_IN2 = 5.01 MHz, both tones at –6-dBFS amplitude, input to single channel		–70	dBc
Δ_IQG	I/Q channel gain matching	16X and 8X CW clock mode		±0.06	dB
Δ_IQG	I/Q channel gain matching	4X CW clock mode		±0.08	dB
Δ_IQP	I/Q channel phase matching	16X and 8X CW clock mode		±0.05	Degrees
Δ_IQP	I/Q channel phase matching	4X CW clock mode		±0.15	Degrees
IM_REJ	Image rejection ratio	16X and 8X CW clock mode		–49	dBc
IM_REJ	Image rejection ratio	4X CW clock mode		–46	dBc
G_LNACW	LNA gain in CW mode			18	dB
HPF_CW	High-pass filter	–1-dB cutoff frequency across LNA_HPF_PROG register settings; see register 199		75	kHz
				150
				300
				600
POWER DISSIPATION
P_CW/Ch	Power dissipation per channel (CW mode)	CW mode, CW_CLK1X = 5 MHz, CW_CLK_NX = 80 MHz	No signal	60	mW/Ch
P_CW/Ch	Power dissipation per channel (CW mode)	CW mode, CW_CLK1X = 5 MHz, CW_CLK_NX = 80 MHz	300-mV_PP input signal to all 16 channels	68	mW/Ch
I_{A_1P9}	AVDD_1P9 current (1.9 V)⁽⁴⁾	CW mode, CW_CLK1X = 5 MHz, CW_CLK_NX = 80 MHz	No signal	385	mA
I_{A_1P9}	AVDD_1P9 current (1.9 V)⁽⁴⁾	CW mode, CW_CLK1X = 5 MHz, CW_CLK_NX = 80 MHz	300-mV_PP input signal to all 16 channels	450	mA
I_{A_3P15}	AVDD_3P15 current⁽⁴⁾	CW mode, CW_CLK1X = 5 MHz, CW_CLK_NX = 80 MHz	No signal	70	mA
I_{A_3P15}	AVDD_3P15 current⁽⁴⁾	CW mode, CW_CLK1X = 5 MHz, CW_CLK_NX = 80 MHz	300-mV_PP input signal to all 16 channels	70	mA
AC PERFORMANCE (Power)
PSRR_{1 kHz}	AC power-supply rejection ratio: tone at output relative to tone on supply	100 mV_PP, 1-kHz tone on supply	AVDD_1P9	–60	dBc
PSRR_{1 kHz}		100 mV_PP, 1-kHz tone on supply	AVDD_3P15	–75	dBc
PSMR_{1 kHz}	AC power-supply modulation ratio: intermodulation tone at output resulting from tones at supply and input measured relative to input tone	100 mV_PP, 1-kHz tone on supply and –1-dBFS, 5-MHz tone at input	AVDD_1P9	–50	dBc
PSMR_{1 kHz}			AVDD_3P15	–50	dBc

(1) NF is measured as the SNR at the output of the device relative to the SNR at the input resulting from ths noise of source resistance R_S.

8.7 Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. Typical values are at T_A = 25°C, minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = 85°C, AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, external differential load resistance between the LVDS output pair, and R_LOAD = 100 Ω, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS (PDN_FAST, PDN_GBL, RESET, SCLK, SDIN, SEN, TGC_PROF<1>, TGC_PROF<2>, TGC_SLOPE, TGC_UP_DN, TR_EN<1>, TR_EN<2>, TR_EN<3>, TR_EN<4>, TX_TRIG)⁽¹⁾
V_IH	High-level input voltage		0.75 × max [AVDD_ 1P9, DVDD_1P8]			V
V_IL	Low-level input voltage			0.25 × min [AVDD_ 1P9, DVDD_1P8]		V
I_IH	High-level input current			150		µA
I_IL	Low-level input current			150		µA
C_i	Input capacitance			8		pF
DIGITAL OUTPUTS (SDOUT)⁽¹⁾
V_OH	High-level output voltage		1.6	1.8⁽²⁾		V
V_OL	Low-level output voltage			0	0.2	V
z_o	Output impedance			50		Ω
LVDS DIGITAL OUTPUTS (DOUT)⁽¹⁾
\|V_OD\|	Output differential voltage	100-Ω external load connected differentially across DOUT	320	400	480	mV
V_OS	Output offset voltage (common-mode voltage of DOUTP_I and DOUTM_I)	100-Ω external load connected differentially across DOUT	0.9	1.03	1.15	V

(1) All digital specifications are characterized across operating temperature range but are not tested at production.

(2) When SDOUT operation is performed in VCA die, typical output voltage of SDOUT is 1.9 V.

8.8 Output Interface Timing Requirements

Typical values are at T_A = 25°C, AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, differential ADC clock, LVDS load C_LOAD = 5 pF, R_LOAD = 100 Ω, 14-bit ADC resolution, and sample rate = 65 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = 85°C.

			MIN	TYP	MAX	UNIT
GENERAL
t_AP	Aperture delay⁽³⁾			1.6		ns
δt_AP	Aperture delay variation from device to device (at same temperature and supply)			±0.5		ns
t_APJ	Aperture jitter with LVPECL clock as input clock			0.5		ps
ADC TIMING
C_d	ADC latency	Default after reset⁽³⁾		8.5		ADC clocks
C_d	ADC latency	Low-latency mode		4.5		ADC clocks
LVDS TIMING⁽¹⁾
f_F	Frame clock frequency⁽³⁾			f_CLKIN		MHz
D_FRAME	Frame clock duty cycle			50%
N_SER	Number of bits serialization of each ADC word		12		16	Bits
f_D	Output rate of serialized data	1X output data rate mode		N_SER × f_CLKIN	1000	Mbps
f_D	Output rate of serialized data	2X output data rate mode		2 × N_SER × f_CLKIN	1000	Mbps
f_B	Bit clock frequency			f_D / 2	500	MHz
D_BIT	Bit clock duty cycle			50%
t_D	Data bit duration⁽³⁾		1	1000 / f_D		ns
t_PDI	Clock propagation delay⁽³⁾			6 × t_D+ 5		ns
δt_PROP	Clock propagation delay variation from device to device (at same temperature and supply)			±2		ns
t_ORF	DOUT, DCLK, FCLK rise and fall time, transition time between –100 mV and +100 mV			0.2		ns
t_OSU	Minimum serial data, serial clock setup time⁽³⁾			t_D / 2 – 0.4		ns
t_OH	Minimum serial data, serial clock hold time⁽³⁾			t_D / 2 – 0.4		ns
t_DV	Minimum data valid window⁽²⁾⁽³⁾			t_D – 0.65		ns
TX_TRIG TIMING
t_{TX_TRIG_DEL}	Delay between TX_TRIG and TX_TRIGD⁽⁴⁾		0.5	0.4 × t_S⁽⁵⁾		ns
t_{SU_TX_TRIGD}	Setup time related to latching TX_TRIG relative to the rising edge of the system clock			0.6		ns
t_{H_TX_TRIGD}	Hold time related to latching TX_TRIG relative to the rising edge of the system clock			0.4		ns

(1) All LVDS specifications are characterized but are not tested at production.

(2) The specification for the minimum data valid window is larger than the sum of the minimum setup and hold times because there can be a skew between the ideal transitions of the serial output data with respect to the transition of the bit clock. This skew can vary across channels and across devices. A mechanism to correct this skew can therefore improve the setup and hold timing margins. For example, the LVDS_DCLK_DELAY_PROG control can be used to shift the relative timing of the bit clock with respect to the data.

(3) See Figure 1.

(4) TX_TRIGD is the internally delayed version of TX_TRIG that gets latched on the rising edge of the ADC clock.

(5) t_S is the ADC clock period in nanoseconds (ns).

8.9 Serial Interface Timing Requirements⁽¹⁾

Typical values are at T_A= 25°C, AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, and DVDD_1P8 = 1.8 V, unless otherwise noted. Minimum and maximum values are across the full temperature range of T_MIN = –40°C to T_MAX = 85°C.

		MIN	TYP	MAX	UNIT
t_SCLK⁽²⁾	SCLK period	50			ns
t_{SCLK_H}⁽²⁾	SCLK high time	20			ns
t_{SCLK_L}⁽²⁾	SCLK low time	20			ns
t_DSU⁽²⁾	Data setup time	5			ns
t_DH⁽²⁾	Data hold time	5			ns
t_{SEN_SU}⁽²⁾	SEN falling edge to SCLK rising edge	8			ns
t_{SEN_HO}⁽²⁾	Time between last SCLK rising edge to SEN rising edge	8			ns
t_{OUT_DV}⁽³⁾	SDOUT delay	12	20	28	ns

(1) All serial interface timing specifications are characterized but are not tested at production.

(2) See Figure 100 for more details.

(3) See Figure 101 for more details.

Figure 1. LVDS Output Timing Specification

8.10 Typical Characteristics: TGC Mode

At T_A = 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, and DVDD_1P8 = 1.8 V. Input to the device: input signal is ac-coupled to INP with a 10-nF capacitor and is applied with source resistance R_S = 50 Ω at frequency f_IN = 5 MHz, and a 50-MHz differential clock is applied on ADC_CLK. Device settings: gain code = 319 (total gain = 45 dB), LPF filter cutoff frequency = 15 MHz, low-noise mode, 14-bit ADC resolution, LVDS interface to capture ADC data, output amplitude V_OUT = –1 dBFS, and SNR is measured from 750 kHz to Nyquist bandwidth. Minimum and maximum values are specified across the full temperature range.

Across power modes

Figure 2. Gain vs Gain Code

Gain = 14 dB (14288 channels)

Figure 4. Gain Matching Histogram

Gain = 38 dB (14288 channels)

Figure 6. Gain Matching Histogram

Gain = 14 dB (14288 channels)

Figure 8. Output Offset Histogram

Figure 10. Input Impedance Magnitude vs Frequency

Across LPF corner settings

Figure 12. Full-Channel, Amplitude Response vs
Frequency

Across INM capacitor

Figure 14. Full-Channel, Low-Frequency Amplitude Response vs Frequency

Across power modes

Figure 16. Input-Referred Noise vs Gain Code (Zoomed)

Across LNA HPF corner settings

Figure 18. Low-Frequency, Output-Referred Noise vs Frequency

Figure 20. Input-Referred Noise vs Frequency

Across power modes

Figure 22. Signal-to-Noise Ratio vs Gain

Across power modes

Figure 24. Second-Order Harmonic Distortion vs Frequency

Across power modes

Figure 26. Second-Order Harmonic Distortion vs Gain

f_OUT1 = –1 dBFS, f_OUT2 = –21 dBFS

Figure 28. IMD3 vs Gain

Across gain codes

Figure 30. AVDD_1P9 Power-Supply Modulation Ratio vs
100-mV_PP Supply Noise Frequencies

Across gain codes

Figure 32. AVDD_1P9 Power-Supply Rejection Ratio vs
100-mV_PP Supply Noise Frequencies

Figure 34. Output and Gain Code Step Response vs Time

Figure 36. Pulse Inversion Asymmetrical Input vs Time

For the input in Figure 36, gain = 21 dB, across positive and negative overload

Figure 38. Device Pulse Inversion Output vs Time (Zoomed)

V_IN = large amplitude (50 mV_PP)
followed by small amplitude (500 µV_PP)

Figure 40. Output Code Overload Recovery vs Time (Zoomed)

Across power modes

Figure 42. Device Power vs Gain Code

Across ADC resolution

Figure 44. ADC Power vs ADC Sample Rate

Across power modes

Figure 46. AVDD_3P15 Supply Current vs Gain Code

Across temperature

Figure 3. Gain vs Gain Code

Gain = 30 dB (14288 channels)

Figure 5. Gain Matching Histogram

Gain = 45 dB (14288 channels)

Figure 7. Gain Matching Histogram

Gain = 45 dB (14288 channels)

Figure 9. Output Offset Histogram

Figure 11. Input Impedance Phase vs Frequency

Across LNA HPF corner settings

Figure 13. Full-Channel, Low-Frequency Amplitude Response vs Frequency

Across power modes

Figure 15. Input-Referred Noise vs Gain Code

Across power modes

Figure 17. Output-Referred Noise vs Gain Code

With INMx capacitor = 1 µF

Figure 19. Low-Frequency, Output-Referred Noise vs Frequency

Figure 21. Output-Referred Noise vs Frequency

Across power modes

Figure 23. Noise Figure vs Source Impedance

Across power modes

Figure 25. Third-Order Harmonic Distortion vs Frequency

Across power modes

Figure 27. Third-Order Harmonic Distortion vs Gain

f_OUT1 = –7 dBFS, f_OUT2 = –7 dBFS

Figure 29. IMD3 vs Gain

Across gain codes

Figure 31. AVDD_3P15 Power-Supply Modulation Ratio vs
100-mV_PP Supply Noise Frequencies

Across gain codes

Figure 33. AVDD_3P15 Power-Supply Rejection Ratio vs
100-mV_PP Supply Noise Frequencies

Figure 35. Output and Gain Code Step Response vs Time

For the input in Figure 36, gain = 21 dB, across positive and negative overload

Figure 37. Device Pulse Inversion Output vs Time

V_IN = large amplitude (50 mV_PP)
followed by small amplitude (500 µV_PP)

Figure 39. Output Code Overload Recovery vs Time

Across digital HPF corner settings

Figure 41. Digital High-Pass Filter Gain Response vs Frequency

Across power modes

Figure 43. VCA Power vs Gain Code

Across power modes

Figure 45. AVDD_1P9 Supply Current vs Gain Code

12-bit resolution

Figure 47. AVDD_1P8, DVDD_1P8 and DVDD_1P2 Supply Current vs ADC Sample Rate

14-bit resolution

Figure 48. AVDD_1P8, DVDD_1P8 and DVDD_1P2 Supply Current vs ADC Sample Rate

For all power modes

Figure 49. Total Power Dissipation vs ADC Sample Rate

8.11 Typical Characteristics: CW Mode

At T_A = 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, and DVDD_1P8 = 1.8 V. Input to the device: input signal = 2 MHz, CW_CLK1X = 2-MHz differential, and CW_CLK_NX = 32-MHz differential. Device settings: CW clock mode = 16X, and 1X and 16X clock buffer in differential mode, and ADC in power-down mode. Minimum and maximum values are specified across the full temperature range.

Across LNA HPF corner settings

Figure 50. Full-Channel, Low-Frequency Amplitude Response vs Frequency

f_IN = 2 MHz, across one channel and 16 channels

Figure 52. CW Phase Noise vs Frequency

Across all CW clock modes

Figure 54. AVDD_1P9 and AVDD_3P15 Supply Current vs CW Clock Frequency

f_IN = 2 MHz, one channel across CW clock modes

Figure 51. CW Phase Noise vs Frequency

f_IN = 2 MHz, 16 channels across CW clock modes

Figure 53. CW Phase Noise vs Frequency

Figure 55. Power vs CW 1X Clock Frequency

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8 Specifications

8.1 Absolute Maximum Ratings

8.2 ESD Ratings

8.3 Recommended Operating Conditions

8.4 Thermal Information

8.5 Electrical Characteristics: TGC Mode

8.6 Electrical Characteristics: CW Mode

8.7 Digital Characteristics

8.8 Output Interface Timing Requirements

8.9 Serial Interface Timing Requirements(1)

8.10 Typical Characteristics: TGC Mode

8.11 Typical Characteristics: CW Mode

8.9 Serial Interface Timing Requirements⁽¹⁾