SBAS688E April   2015  – September 2017 AFE5816

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Family Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: TGC Mode
    6. 8.6  Electrical Characteristics: CW Mode
    7. 8.7  Digital Characteristics
    8. 8.8  Output Interface Timing Requirements
    9. 8.9  Serial Interface Timing Requirements
    10. 8.10 Typical Characteristics: TGC Mode
    11. 8.11 Typical Characteristics: CW Mode
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Attenuator
        1. 9.3.1.1 Implementation
        2. 9.3.1.2 Maximum Signal Amplitude Support
        3. 9.3.1.3 Attenuator High-Pass Filter (ATTEN HPF)
      2. 9.3.2  Low-Noise Amplifier (LNA)
        1. 9.3.2.1 Input Signal Support in TGC Mode
        2. 9.3.2.2 Input Signal Support in CW Mode
        3. 9.3.2.3 Input Circuit
        4. 9.3.2.4 LNA High-Pass Filter (LNA HPF)
          1. 9.3.2.4.1 Disconnecting the LNA HPF During Overload
        5. 9.3.2.5 LNA Noise Contribution
      3. 9.3.3  High-Pass Filter (HPF)
      4. 9.3.4  Low-Pass Filter (LPF)
      5. 9.3.5  Digital TGC (DTGC)
        1. 9.3.5.1 DTGC Overview
        2. 9.3.5.2 DTGC Programming
          1. 9.3.5.2.1 DTGC Profile
            1. 9.3.5.2.1.1 Profile Selection
        3. 9.3.5.3 DTGC Modes
          1. 9.3.5.3.1 Programmable Fixed-Gain Mode
          2. 9.3.5.3.2 Up, Down Ramp Mode
          3. 9.3.5.3.3 External Non-Uniform Mode
          4. 9.3.5.3.4 Internal Non-Uniform Mode
            1. 9.3.5.3.4.1 Memory
              1. 9.3.5.3.4.1.1 Write Operation for the Memory
              2. 9.3.5.3.4.1.2 Read Operation for the Memory
            2. 9.3.5.3.4.2 Gain Curve Description for the Internal Non-Uniform Mode
        4. 9.3.5.4 Timing Specifications
      6. 9.3.6  Continuous-Wave (CW) Beamformer
        1. 9.3.6.1 16 × ƒcw Mode
        2. 9.3.6.2 8 × ƒcw and 4 × ƒcw Modes
        3. 9.3.6.3 1 × ƒcw Mode
        4. 9.3.6.4 CW Clock Selection
        5. 9.3.6.5 CW Supporting Circuits
      7. 9.3.7  Analog-to-Digital Converter (ADC)
        1. 9.3.7.1 System Clock Input
        2. 9.3.7.2 System Clock Configuration for Multiple Devices
      8. 9.3.8  LVDS Interface
        1. 9.3.8.1 LVDS Buffer
        2. 9.3.8.2 LVDS Data Rate Modes
          1. 9.3.8.2.1 1X Data Rate Mode
          2. 9.3.8.2.2 2X Data Rate Mode
      9. 9.3.9  ADC Register, Digital Processing Description
        1. 9.3.9.1 Digital Offset
          1. 9.3.9.1.1 Manual Offset Correction
          2. 9.3.9.1.2 Auto Offset Correction Mode (Offset Correction using a Built-In Offset Calculation Function)
        2. 9.3.9.2 Digital Average
        3. 9.3.9.3 Digital Gain
        4. 9.3.9.4 Digital HPF
        5. 9.3.9.5 LVDS Synchronization Operation
      10. 9.3.10 Power Management
        1. 9.3.10.1 Voltage-Controlled Attenuator (VCA) Power Management
        2. 9.3.10.2 Analog-to-Digital Converter (ADC) Power Management
    4. 9.4 Device Functional Modes
      1. 9.4.1 ADC Test Pattern Mode
        1. 9.4.1.1 Test Patterns
          1. 9.4.1.1.1 LVDS Test Pattern Mode
      2. 9.4.2 Partial Power-Up and Power-Down Mode
      3. 9.4.3 Global Power-Down Mode
      4. 9.4.4 TGC Configuration
      5. 9.4.5 Digital TGC Test Modes
        1. 9.4.5.1 ENABLE_INT_START and NEXT_CYCLE_WAIT_TIME
        2. 9.4.5.2 MANUAL_START
        3. 9.4.5.3 FLIP_ATTEN
        4. 9.4.5.4 DIS_ATTEN
        5. 9.4.5.5 Fixed Attenuation Mode
      6. 9.4.6 CW Configuration
      7. 9.4.7 TGC + CW Mode
    5. 9.5 Programming
      1. 9.5.1 Serial Peripheral Interface (SPI) Operation
        1. 9.5.1.1 Serial Register Write Description
        2. 9.5.1.2 Register Readout
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Do's and Don'ts
    4. 10.4 Initialization Set Up
  11. 11Power Supply Recommendations
    1. 11.1 Power Sequencing and Initialization
      1. 11.1.1 Power Sequencing
      2. 11.1.2 PLL Initialization
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Power Supply, Grounding, and Bypassing
      2. 12.1.2 Board Layout
    2. 12.2 Layout Example
  13. 13Register Maps
    1. 13.1 Serial Register Map
      1. 13.1.1 Global Register Map
        1. 13.1.1.1 Description of Global Register
          1. 13.1.1.1.1 Register 0 (address = 0h)
      2. 13.1.2 ADC Register Map
        1. 13.1.2.1 Description of ADC Registers
          1. 13.1.2.1.1  Register 1 (address = 1h)
          2. 13.1.2.1.2  Register 2 (address = 2h)
          3. 13.1.2.1.3  Register 3 (address = 3h)
          4. 13.1.2.1.4  Register 4 (address = 4h)
          5. 13.1.2.1.5  Register 5 (address = 5h)
          6. 13.1.2.1.6  Register 7 (address = 7h)
          7. 13.1.2.1.7  Register 8 (address = 8h)
          8. 13.1.2.1.8  Register 11 (address = Bh)
          9. 13.1.2.1.9  Register 13 (address = Dh)
          10. 13.1.2.1.10 Register 14 (address = Eh)
          11. 13.1.2.1.11 Register 15 (address = Fh)
          12. 13.1.2.1.12 Register 16 (address = 10h)
          13. 13.1.2.1.13 Register 17 (address = 11h)
          14. 13.1.2.1.14 Register 18 (address = 12h)
          15. 13.1.2.1.15 Register 19 (address = 13h)
          16. 13.1.2.1.16 Register 20 (address = 14h)
          17. 13.1.2.1.17 Register 21 (address = 15h)
          18. 13.1.2.1.18 Register 23 (address = 17h)
          19. 13.1.2.1.19 Register 24 (address = 18h)
          20. 13.1.2.1.20 Register 25 (address = 19h)
          21. 13.1.2.1.21 Register 26 (address = 1Ah)
          22. 13.1.2.1.22 Register 27 (address = 1Bh)
          23. 13.1.2.1.23 Register 28 (address = 1Ch)
          24. 13.1.2.1.24 Register 29 (address = 1Dh)
          25. 13.1.2.1.25 Register 30 (address = 1Eh)
          26. 13.1.2.1.26 Register 31 (address = 1Fh)
          27. 13.1.2.1.27 Register 32 (address = 20h)
          28. 13.1.2.1.28 Register 33 (address = 21h)
          29. 13.1.2.1.29 Register 35 (address = 23h)
          30. 13.1.2.1.30 Register 36 (address = 24h)
          31. 13.1.2.1.31 Register 37 (address = 25h)
          32. 13.1.2.1.32 Register 38 (address = 26h)
          33. 13.1.2.1.33 Register 39 (address = 27h)
          34. 13.1.2.1.34 Register 40 (address = 28h)
          35. 13.1.2.1.35 Register 41 (address = 29h)
          36. 13.1.2.1.36 Register 42 (address = 2Ah)
          37. 13.1.2.1.37 Register 43 (address = 2Bh)
          38. 13.1.2.1.38 Register 44 (address = 2Ch)
          39. 13.1.2.1.39 Register 45 (address = 2Dh)
          40. 13.1.2.1.40 Register 47 (address = 2Fh)
          41. 13.1.2.1.41 Register 48 (address = 30h)
          42. 13.1.2.1.42 Register 49 (address = 31h)
          43. 13.1.2.1.43 Register 50 (address = 32h)
          44. 13.1.2.1.44 Register 51 (address = 33h)
          45. 13.1.2.1.45 Register 52 (address = 34h)
          46. 13.1.2.1.46 Register 53 (address = 35h)
          47. 13.1.2.1.47 Register 54 (address = 36h)
          48. 13.1.2.1.48 Register 55 (address = 37h)
          49. 13.1.2.1.49 Register 56 (address = 38h)
          50. 13.1.2.1.50 Register 57 (address = 39h)
          51. 13.1.2.1.51 Register 59 (address = 3Bh)
          52. 13.1.2.1.52 Register 60 (address = 3Ch)
          53. 13.1.2.1.53 Register 65 (address = 41h)
          54. 13.1.2.1.54 Register 66 (address = 42h)
          55. 13.1.2.1.55 Register 67 (address = 43h)
      3. 13.1.3 VCA Register Map
        1. 13.1.3.1 Description of VCA Registers
          1. 13.1.3.1.1  Register 192 (address = C0h)
          2. 13.1.3.1.2  Register 193 (address = C1h)
          3. 13.1.3.1.3  Register 194 (address = C2h)
          4. 13.1.3.1.4  Register 195 (address = C3h)
          5. 13.1.3.1.5  Register 196 (address = C4h)
          6. 13.1.3.1.6  Register 197 (address = C5h)
          7. 13.1.3.1.7  Register 198 (address = C6h)
          8. 13.1.3.1.8  Register 199 (address = C7h)
          9. 13.1.3.1.9  Register 200 (address = C8h)
          10. 13.1.3.1.10 Register 206 (address = CEh)
          11. 13.1.3.1.11 Register 230 (address = E6h)
      4. 13.1.4 DTGC Register Map
        1. 13.1.4.1 Description of DTGC Register
          1. 13.1.4.1.1 DTGC Registers
            1. 13.1.4.1.1.1  Register 1 (address = 1h)
            2. 13.1.4.1.1.2  Registers 2-160 (address = 2h-A0h)
            3. 13.1.4.1.1.3  Register 161 (address = A1h)
            4. 13.1.4.1.1.4  Register 162 (address = A2h)
            5. 13.1.4.1.1.5  Register 163 (address = A3h)
            6. 13.1.4.1.1.6  Register 164 (address = A4h)
            7. 13.1.4.1.1.7  Register 165 (address = A5h)
            8. 13.1.4.1.1.8  Register 166 (address = A6h)
            9. 13.1.4.1.1.9  Register 167 (address = A7h)
            10. 13.1.4.1.1.10 Register 168 (address = A8h)
            11. 13.1.4.1.1.11 Register 169 (address = A9h)
            12. 13.1.4.1.1.12 Register 170 (address = AAh)
            13. 13.1.4.1.1.13 Register 171 (address = ABh)
            14. 13.1.4.1.1.14 Register 172 (address = ACh)
            15. 13.1.4.1.1.15 Register 173 (address = ADh)
            16. 13.1.4.1.1.16 Register 174 (address = AEh)
            17. 13.1.4.1.1.17 Register 175 (address = AFh)
            18. 13.1.4.1.1.18 Register 176 (address = B0h)
            19. 13.1.4.1.1.19 Register 177 (address = B1h)
            20. 13.1.4.1.1.20 Register 178 (address = B2h)
            21. 13.1.4.1.1.21 Register 179 (address = B3h)
            22. 13.1.4.1.1.22 Register 180 (address = B4h)
            23. 13.1.4.1.1.23 Register 181 (address = B5h)
            24. 13.1.4.1.1.24 Register 182 (address = B6h)
            25. 13.1.4.1.1.25 Register 183 (address = B7h)
            26. 13.1.4.1.1.26 Register 185 (address = B9h)
            27. 13.1.4.1.1.27 Register 186 (address = BAh)
  14. 14Device and Documentation Support
    1. 14.1 Documentation Support
      1. 14.1.1 Related Documentation
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range, unless otherwise noted(1)
MIN MAX UNIT
Supply voltage range AVDD_1P8 –0.3 2.2 V
AVDD_1P9 –0.3 2.2
AVDD_3P15 –0.3 3.9
DVDD_1P2 –0.3 1.35
DVDD_1P8 –0.3 2.2
Voltage at analog inputs –0.3 Minimum [2.2,
(AVDD_1P9 + 0.3)]
V
Voltage at digital inputs –0.3 Minimum [2.2, (AVDD_1P9 + 0.3), (DVDD_1P8 + 0.3)] V
Temperature Maximum junction temperature (TJ),
any condition
105 °C
Storage, Tstg –55 150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range, unless otherwise noted
PARAMETER MIN TYP MAX UNIT
SUPPLIES
VA_1P8 AVDD_1P8 voltage 1.7 1.8 1.9 V
VA_1P9 AVDD_1P9 voltage Low-noise mode, medium-power mode 1.8 1.9 2.0 V
Low-power mode 1.75 1.8 2.0
VA_3P15 AVDD_3P15 voltage 3 3.15 3.3 V
VD_1P2 DVDD_1P2 voltage 1.15 1.2 1.25 V
VD_1P8 DVDD_1P8 voltage 1.7 1.8 1.9 V
TEMPERATURE
TA Ambient temperature –40 85 °C
BIAS VOLTAGES
Common-mode voltage(1) ADC_CLKP, ADC_CLKM in differential mode 0.7 V
CLKP_1X, CLKM_1X, CLKP_16X, CLKM_16X in differential mode 1.5
CW_IP_OUTP, CW_IP_OUTM, CW_QP_OUTP, CW_QP_OUTM 0.9
(INM1, INP1), (INM2, INP2)…(INM16, INP16) 1
Bias voltage(1) BAND_GAP 1.2 V
BIAS_2P5 2.5
LNA_INCM 1
SRC_BIAS 0.5
ADC CLOCK INPUT: ADC_CLK
fCLKIN ADC clock frequency 14-bit ADC resolution 5 65 MHz
12-bit ADC resolution 5 80
VDEADC Differential clock amplitude Sine-wave, ac-coupled 0.7 VPP
LVPECL, ac-coupled 1.6
LVDS, ac-coupled 0.7
VSEADC Single-ended clock amplitude LVCMOS on ADC_CLKP with ADC_CLKM grounded 1.8 V
DADC ADC_CLK duty cycle 40% 50% 60%
CW CLOCK INPUT: CW_CLK1X, CW_CLK_NX
CWCLK CW clock frequency CW_CLK1X across CW clock modes in relation to CW_CLK1X; see the CW_CLK_MODE register bits in register 192 8 MHz
CW_CLK_NX across CW clock modes; see the CW_CLK_MODE register bits in register 192 16X mode 16X CW_
CLK1X
8X mode 8X
4X mode 4X
VDECW Differential clock amplitude CW_CLK1X, CW_CLK_NX. LVDS, ac-coupled 0.7 VPP
VSECW Single-ended clock amplitude LVCMOS on CLKP_1X, CLKP_16X with CLKM_1X, CLKM_16X grounded or floating 3.15 V
DCW CLK duty cycle CW_CLK1X, CW_CLK_NX 40% 50% 60%
DIGITAL OUTPUT (LVDS)
RL Differential load resistance 100 Ω
Internally set by the device.

Thermal Information

THERMAL METRIC(1) AFE5816 UNIT
ZAV (NFBGA)
289 PINS
RθJA Junction-to-ambient thermal resistance 26.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 5.6 °C/W
RθJB Junction-to-board thermal resistance 11.7 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 11.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics: TGC Mode

At TA = 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, and DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V. Input to the device: input signal is ac-coupled to INP with a 10-nF capacitor and is applied with source resistance RS = 50 Ω at frequency fIN = 5 MHz, and a 50-MHz differential clock is applied on ADC_CLK. Device settings: gain code = 319 (total gain = 45 dB), 14-bit ADC resolution, LVDS interface to capture ADC data, and output amplitude VOUT = –1 dBFS. Minimum and maximum values are specified across the full temperature range.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
GENERAL
VMAX Maximum linear input voltage At INP_SOURCE node; see the Functional Block Diagram section 1 VPP
At INPx node; see the Functional Block Diagram section 0.4
CINP Input capacitance 35 pF
GCODE Gain code(1) Programs the total gain 0 319
GTOT Total gain Low-noise mode and medium-power mode (6 + 0.125 × GCODE) dB
Low-power mode (12 + 0.125 × GCODE)
GRANGE Gain range 39 dB
GSLOPE Gain slope 0.125 dB/GCODE
TTGC TGC response time GCODE changed from 64 to 319 10 µs
VN,IRN Input voltage noise RS = 0 Ω, calculated in band of 4-MHz to 6-MHz frequency Low-noise mode 1 nV/√Hz
Medium-power mode 1.3
Low-power mode 1.45
IN,IRN Input-referred current noise Across low-noise, medium-power, and low-power mode 1.2 pA/√Hz
NF Noise figure(3) RS = 50 Ω Low-noise mode 3.6 dB
Medium-power mode 4.5
Low-power mode 5.0
RS = 400 Ω Low-noise mode 1.2 dB
Medium-power mode 1.5
Low-power mode 1.6
GENERAL (continued)
KCORR Channel-to-channel noise correlation factor(2) Without a signal, calculated in a 1-MHz to 10-MHz bandwidth RS = 330 Ω –20 dB
RS = 100 Ω –26
With a signal, calculated in a 1-MHz to 10-MHz bandwidth Total gain = 45 dB –17
Total gain = 26 dB –14
With a signal, calculated in a 1-MHz bandwidth around a 5-MHz input signal frequency Total gain = 45 dB –13
Total gain = 26 dB –10
SNR Signal-to-noise ratio SNR calculated in 750 kHz to Nyquist bandwidth Total gain = 14 dB 65 68 dBFS
Total gain = 45 dB 55 58
SNRNB Narrow-band SNR SNR calculated in 2-MHz bandwidth around input signal frequency Total gain = 30 dB 72.5 76 dBFS
LPF 3rd-order, low-pass filter –3-dB cutoff frequency across LPF_PROG register settings;
see register 199
Low-noise and medium-power mode 10 MHz
15
20
25
Low-power mode 5
7.5
10
12.5
ΔLPF LPF bandwidth variation ±5%
ΔGr Channel-to-channel group delay matching 2-MHz to 15-MHz input signal frequency 2 ns
Δφ Channel-to-channel phase matching 15-MHz signal 11 Degrees
GMATCH Gain matching Device-to-device, average across channels GCODE < 64 ±0.5 dB
GCODE > 64 –1 ±0.5 1
Channel-to-channel, same device GCODE < 64 ±0.5
GCODE > 64 –1 ±0.5 1
HD2 Second-order harmonic distortion Output amplitude = –1 dBFS, gain = 45 dB –65 dBc
Output amplitude = –1 dBFS, gain = 6 dB –55
HD3 Third-order harmonic distortion Output amplitude = –1 dBFS, gain = 45 dB –60 dBc
Output amplitude = –1 dBFS, gain = 6 dB –60
THD Total harmonic distortion Output amplitude = –1 dBFS, gain = 45 dB –58 dBc
Output amplitude = –1 dBFS, gain = 6 dB –54
IMD3 Third-order intermodulation distortion Input frequency 1 = 5 MHz at –1 dBFS,
input frequency 2 = 5.01 MHz at –21 dBFS
–75 dBc
XTALK Fundamental crosstalk Signal applied to a single channel. Crosstalk measured on neighboring channel. –55 dBc
PN1kHz Phase noise Calculated at 1-kHz offset from 5-MHz input signal frequency –129 dBc/Hz
VORO Output offset ±600 LSB
GLNA LNA gain range in TGC mode 14 to 45 dB
GENERAL (continued)
HPFTGC LNA High-pass filter –1-dB cutoff frequency across LNA_HPF_PROG register settings;
see register 199
75 kHz
150
300
600
ADC SPECIFICATIONS
fS Sample rate 14-bit resolution 5 65 MSPS
12-bit resolution 5 80
SNR Signal-to-noise ratio 14-bit resolution Without a signal 75 dBFS
With a –1-dBFS signal amplitude 72.5
12-bit resolution Without a signal 72
With a –1-dBFS signal amplitude 69.5
VMAX,ADC ADC input full-scale range 2 VPP
POWER DISSIPATION
PTGC/Ch Power dissipation per channel: 12-bit ADC resolution and 80-MSPS ADC clock TGC low-noise mode, 500-mVPP input signal up to 1% duty cycle applied to 16 channels 94 mW/Ch
TGC medium-power mode, 500-mVPP input signal up to 1% duty cycle applied to 16 channels 72
TGC low-power mode, 500-mVPP input signal up to 1% duty cycle applied to 16 channels 62
IA_1P9 AVDD_1P9 current (1.9 V)(4) TGC low-noise mode, 500-mVPP input signal up to 1% duty cycle applied to 16 channels 430 mA
TGC medium-power mode, 500-mVPP input signal up to 1% duty cycle applied to 16 channels 240
TGC low-power mode, 500-mVPP input signal up to 1% duty cycle applied to 16 channels 160
IA_3P15 AVDD_3P15 current(4) TGC low-noise, medium-power, and low-power modes, 500-mVPP input signal up to 1% duty cycle applied to 16 channels 20 mA
IA_1P8 AVDD_1P8 current(4) For a 12-bit ADC resolution and an 80-MSPS system clock 170 mA
ID_1P2 DVDD_1P2 current(4) For a 12-bit ADC resolution and an 80-MSPS system clock 110 mA
IA_1P8 DVDD_1P8 current(4) For a 12-bit ADC resolution and an 80-MSPS system clock 100 mA
AC PERFORMANCE (Power)
PSRR1 kHz AC power-supply rejection ratio: tone at output relative to tone on supply 100 mVPP, 1-kHz tone on supply AVDD_1P9 –65 dBc
AVDD_3P15 –90
AVDD_1P8, DVDD_1P8, and DVDD_1P2 –70
PSMR1 kHz AC power-supply modulation ratio: intermodulation tone at output resulting from tones at supply and input measured relative to input tone 100 mVPP, 1-kHz tone on supply and –1-dBFS, 5-MHz tone at input AVDD_1P9 –45 dBc
AVDD_3P15 –45
AVDD_1P8, DVDD_1P8, and DVDD_1P2 –80
POWER DOWN
PDOWN Power dissipation in
power-down mode
Partial power-down when PDN_FAST = high 17 mW/Ch
Complete power-down when PDN_GBL = high 3
tUP Power-up time Partial power-down when PDN_FAST = high and the device is in partial power-down time for < 500 µs 3 µs
Complete power-down when PDN_GBL = high 1 ms
The gain code range from 0 to 63 controls the input attenuation and the gain code range from 64 to 319 controls the LNA gain.
The noise-correlation factor is defined as 10 × log10[Nc / (Nc + Nu)], where Nc is the correlated noise power in a single channel and Nu is the uncorrelated noise power in a single channel. The noise-correlation factor measurement is described by the equation: AFE5816 noise_corelation_eq.gif
where N_16CH is the noise power of the summed 16 channels and N_1CH is the noise power of one channel.
NF is measured as the SNR at the output of the device relative to the SNR at the input resulting from ths noise of source resistance RS.
Designing the power supply with 2X of the typical current capacity is recommended to take care of current variation across devices, switching current, signal current, and so forth.

Electrical Characteristics: CW Mode

At TA = 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, and DVDD_1P8 = 1.8 V. Input to the device: input signal is ac-coupled to INP with a 10-nF capacitor and is applied with source resistance RS = 50 Ω at frequency fIN = 2 MHz, CW_CLK1X = 2-MHz differential clock, and CW_CLK_NX = 32-MHz differential clock. Device settings: CW clock mode = 16X, and 1X and 16X clock buffer in differential mode and ADC in power-down mode. Minimum and maximum values are specified across the full temperature range.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
VMAX, CW Maximum input swing 300 mVPP
RV2I Voltage-to-current resistor at LNA output 500 Ω
IOPP Peak-to-peak output current per channel 4.8 mA/Ch
VN,IRCW Input voltage noise 1 channel 1.55 nV/√Hz
16 channels 0.45
IN,ORCW Output current noise 1 channel 19 pA/√Hz
16 channels 80
NFCW Noise figure(1) RS = 100 Ω, 1 channel 4 dB
RS = 100 Ω, 16 channels 4.8
LCWM CW mixer conversion loss 4 dB
PN1 kHz,CW Phase noise 16X CW clock mode, calculated at 1-kHz frequency Signal to 1 channel –151 dBc/Hz
Signal to 16 channels –161
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 5 MHz, fIN2 = 5.01 MHz, both tones at –6-dBFS amplitude,
input to all the 16 channels.
–60 dBc
fIN1 = 5 MHz, fIN2 = 5.01 MHz, both tones at –6-dBFS amplitude, input to single channel –70
ΔIQG I/Q channel gain matching 16X and 8X CW clock mode ±0.06 dB
4X CW clock mode ±0.08
ΔIQP I/Q channel phase matching 16X and 8X CW clock mode ±0.05 Degrees
4X CW clock mode ±0.15
IMREJ Image rejection ratio 16X and 8X CW clock mode –49 dBc
4X CW clock mode –46
GLNACW LNA gain in CW mode 18 dB
HPFCW High-pass filter –1-dB cutoff frequency across LNA_HPF_PROG register settings; see register 199 75 kHz
150
300
600
POWER DISSIPATION
PCW/Ch Power dissipation
per channel (CW mode)
CW mode, CW_CLK1X = 5 MHz, CW_CLK_NX = 80 MHz No signal 60 mW/Ch
300-mVPP input signal to all 16 channels 68
IA_1P9 AVDD_1P9 current
(1.9 V)(4)
CW mode, CW_CLK1X = 5 MHz, CW_CLK_NX = 80 MHz No signal 385 mA
300-mVPP input signal to all 16 channels 450
IA_3P15 AVDD_3P15 current(4) CW mode, CW_CLK1X = 5 MHz, CW_CLK_NX = 80 MHz No signal 70 mA
300-mVPP input signal to all 16 channels 70
AC PERFORMANCE (Power)
PSRR1 kHz AC power-supply rejection ratio: tone at output relative to tone on supply 100 mVPP, 1-kHz tone on supply AVDD_1P9 –60 dBc
AVDD_3P15 –75
PSMR1 kHz AC power-supply modulation ratio: intermodulation tone at output resulting from tones at supply and input measured relative to input tone 100 mVPP, 1-kHz tone on supply and –1-dBFS, 5-MHz tone at input AVDD_1P9 –50 dBc
AVDD_3P15 –50
NF is measured as the SNR at the output of the device relative to the SNR at the input resulting from ths noise of source resistance RS.

Digital Characteristics

The dc specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1. Typical values are at TA = 25°C, minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C, AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, external differential load resistance between the LVDS output pair, and RLOAD = 100 Ω, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL INPUTS
(PDN_FAST, PDN_GBL, RESET, SCLK, SDIN, SEN, TGC_PROF<1>, TGC_PROF<2>, TGC_SLOPE, TGC_UP_DN, TR_EN<1>, TR_EN<2>, TR_EN<3>, TR_EN<4>, TX_TRIG)(1)
VIH High-level input voltage 0.75 × max [AVDD_
1P9, DVDD_1P8]
V
VIL Low-level input voltage 0.25 × min [AVDD_
1P9, DVDD_1P8]
V
IIH High-level input current 150 µA
IIL Low-level input current 150 µA
Ci Input capacitance 8 pF
DIGITAL OUTPUTS (SDOUT)(1)
VOH High-level output voltage 1.6 1.8(2) V
VOL Low-level output voltage 0 0.2 V
zo Output impedance 50 Ω
LVDS DIGITAL OUTPUTS (DOUT)(1)
|VOD| Output differential voltage 100-Ω external load connected differentially across DOUT 320 400 480 mV
VOS Output offset voltage
(common-mode voltage of DOUTPI and DOUTMI)
100-Ω external load connected differentially across DOUT 0.9 1.03 1.15 V
All digital specifications are characterized across operating temperature range but are not tested at production.
When SDOUT operation is performed in VCA die, typical output voltage of SDOUT is 1.9 V.

Output Interface Timing Requirements

Typical values are at TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, DVDD_1P8 = 1.8 V, differential ADC clock, LVDS load CLOAD = 5 pF, RLOAD = 100 Ω, 14-bit ADC resolution, and sample rate = 65 MSPS, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C.
MIN TYP MAX UNIT
GENERAL
tAP Aperture delay(3) 1.6 ns
δtAP Aperture delay variation from device to device
(at same temperature and supply)
±0.5 ns
tAPJ Aperture jitter with LVPECL clock as input clock 0.5 ps
ADC TIMING
Cd ADC latency Default after reset(3) 8.5 ADC clocks
Low-latency mode 4.5
LVDS TIMING(1)
fF Frame clock frequency(3) fCLKIN MHz
DFRAME Frame clock duty cycle 50%
NSER Number of bits serialization of each ADC word 12 16 Bits
fD Output rate of serialized data 1X output data rate mode NSER × fCLKIN 1000 Mbps
2X output data rate mode 2 × NSER × fCLKIN 1000
fB Bit clock frequency fD / 2 500 MHz
DBIT Bit clock duty cycle 50%
tD Data bit duration(3) 1 1000 / fD ns
tPDI Clock propagation delay(3) 6 × tD+ 5 ns
δtPROP Clock propagation delay variation from device to device (at same temperature and supply) ±2 ns
tORF DOUT, DCLK, FCLK rise and fall time, transition time between –100 mV and +100 mV 0.2 ns
tOSU Minimum serial data, serial clock setup time(3) tD / 2 – 0.4 ns
tOH Minimum serial data, serial clock hold time(3) tD / 2 – 0.4 ns
tDV Minimum data valid window(2)(3) tD – 0.65 ns
TX_TRIG TIMING
tTX_TRIG_DEL Delay between TX_TRIG and TX_TRIGD(4) 0.5 0.4 × tS(5) ns
tSU_TX_TRIGD Setup time related to latching TX_TRIG relative to the rising edge of the system clock 0.6 ns
tH_TX_TRIGD Hold time related to latching TX_TRIG relative to the rising edge of the system clock 0.4 ns
All LVDS specifications are characterized but are not tested at production.
The specification for the minimum data valid window is larger than the sum of the minimum setup and hold times because there can be a skew between the ideal transitions of the serial output data with respect to the transition of the bit clock. This skew can vary across channels and across devices. A mechanism to correct this skew can therefore improve the setup and hold timing margins. For example, the LVDS_DCLK_DELAY_PROG control can be used to shift the relative timing of the bit clock with respect to the data.
See Figure 1.
TX_TRIGD is the internally delayed version of TX_TRIG that gets latched on the rising edge of the ADC clock.
tS is the ADC clock period in nanoseconds (ns).

Serial Interface Timing Requirements(1)

Typical values are at TA = 25°C, AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, and DVDD_1P8 = 1.8 V, unless otherwise noted. Minimum and maximum values are across the full temperature range of TMIN = –40°C to TMAX = 85°C.
MIN TYP MAX UNIT
tSCLK(2) SCLK period 50 ns
tSCLK_H(2) SCLK high time 20 ns
tSCLK_L(2) SCLK low time 20 ns
tDSU(2) Data setup time 5 ns
tDH(2) Data hold time 5 ns
tSEN_SU(2) SEN falling edge to SCLK rising edge 8 ns
tSEN_HO(2) Time between last SCLK rising edge to SEN rising edge 8 ns
tOUT_DV(3) SDOUT delay 12 20 28 ns
All serial interface timing specifications are characterized but are not tested at production.
See Figure 100 for more details.
See Figure 101 for more details.
AFE5816 14b_1x_mode_ots_sbas641.gif Figure 1. LVDS Output Timing Specification

Typical Characteristics: TGC Mode

At TA = 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, and DVDD_1P8 = 1.8 V. Input to the device: input signal is ac-coupled to INP with a 10-nF capacitor and is applied with source resistance RS = 50 Ω at frequency fIN = 5 MHz, and a 50-MHz differential clock is applied on ADC_CLK. Device settings: gain code = 319 (total gain = 45 dB), LPF filter cutoff frequency = 15 MHz, low-noise mode, 14-bit ADC resolution, LVDS interface to capture ADC data, output amplitude VOUT = –1 dBFS, and SNR is measured from 750 kHz to Nyquist bandwidth. Minimum and maximum values are specified across the full temperature range.
AFE5816 D002_SBAS641.gif
Across power modes
Figure 2. Gain vs Gain Code
AFE5816 D004_SBAS641.gif
Gain = 14 dB (14288 channels)
Figure 4. Gain Matching Histogram
AFE5816 D006_SBAS641.gif
Gain = 38 dB (14288 channels)
Figure 6. Gain Matching Histogram
AFE5816 D056_SBAS641.gif
Gain = 14 dB (14288 channels)
Figure 8. Output Offset Histogram
AFE5816 D008_SBAS641.gif
Figure 10. Input Impedance Magnitude vs Frequency
AFE5816 D010_SBAS641.gif
Across LPF corner settings
Figure 12. Full-Channel, Amplitude Response vs
Frequency
AFE5816 D012_SBAS641.gif
Across INM capacitor
Figure 14. Full-Channel, Low-Frequency Amplitude Response vs Frequency
AFE5816 D017_SBAS641.gif
Across power modes
Figure 16. Input-Referred Noise vs Gain Code (Zoomed)
AFE5816 D019_SBAS641.gif
Across LNA HPF corner settings
Figure 18. Low-Frequency, Output-Referred Noise vs Frequency
AFE5816 D021_SBAS641.gif
Figure 20. Input-Referred Noise vs Frequency
AFE5816 D023_SBAS641.gif
Across power modes
Figure 22. Signal-to-Noise Ratio vs Gain
AFE5816 D025_SBAS641.gif
Across power modes
Figure 24. Second-Order Harmonic Distortion vs Frequency
AFE5816 D027_SBAS641.gif
Across power modes
Figure 26. Second-Order Harmonic Distortion vs Gain
AFE5816 D029_SBAS641.gif
fOUT1 = –1 dBFS, fOUT2 = –21 dBFS
Figure 28. IMD3 vs Gain
AFE5816 D031_SBAS641.gif
Across gain codes
Figure 30. AVDD_1P9 Power-Supply Modulation Ratio vs
100-mVPP Supply Noise Frequencies
AFE5816 D033_SBAS641.gif
Across gain codes
Figure 32. AVDD_1P9 Power-Supply Rejection Ratio vs
100-mVPP Supply Noise Frequencies
AFE5816 D035_SBAS641.gif
Figure 34. Output and Gain Code Step Response vs Time
AFE5816 D038_SBAS641.gif
Figure 36. Pulse Inversion Asymmetrical Input vs Time
AFE5816 D041_SBAS641.gif
For the input in Figure 36, gain = 21 dB, across positive and negative overload
Figure 38. Device Pulse Inversion Output vs Time (Zoomed)
AFE5816 D043_SBAS641.gif
VIN = large amplitude (50 mVPP)
followed by small amplitude (500 µVPP)
Figure 40. Output Code Overload Recovery vs Time (Zoomed)
AFE5816 D045_SBAS641.gif
Across power modes
Figure 42. Device Power vs Gain Code
AFE5816 D062_SBAS641.gif
Across ADC resolution
Figure 44. ADC Power vs ADC Sample Rate
AFE5816 D061_SBAS641.gif
Across power modes
Figure 46. AVDD_3P15 Supply Current vs Gain Code
AFE5816 D003_SBAS641.gif
Across temperature
Figure 3. Gain vs Gain Code
AFE5816 D005_SBAS641.gif
Gain = 30 dB (14288 channels)
Figure 5. Gain Matching Histogram
AFE5816 D007_SBAS641.gif
Gain = 45 dB (14288 channels)
Figure 7. Gain Matching Histogram
AFE5816 D057_SBAS641.gif
Gain = 45 dB (14288 channels)
Figure 9. Output Offset Histogram
AFE5816 D009_SBAS641.gif
Figure 11. Input Impedance Phase vs Frequency
AFE5816 D011_SBAS641.gif
Across LNA HPF corner settings
Figure 13. Full-Channel, Low-Frequency Amplitude Response vs Frequency
AFE5816 D016_SBAS641.gif
Across power modes
Figure 15. Input-Referred Noise vs Gain Code
AFE5816 D018_SBAS641.gif
Across power modes
Figure 17. Output-Referred Noise vs Gain Code
AFE5816 D020_SBAS641.gif
With INMx capacitor = 1 µF
Figure 19. Low-Frequency, Output-Referred Noise vs Frequency
AFE5816 D022_SBAS641.gif
Figure 21. Output-Referred Noise vs Frequency
AFE5816 D024_SBAS641.gif
Across power modes
Figure 23. Noise Figure vs Source Impedance
AFE5816 D026_SBAS641.gif
Across power modes
Figure 25. Third-Order Harmonic Distortion vs Frequency
AFE5816 D028_SBAS641.gif
Across power modes
Figure 27. Third-Order Harmonic Distortion vs Gain
AFE5816 D030_SBAS641.gif
fOUT1 = –7 dBFS, fOUT2 = –7 dBFS
Figure 29. IMD3 vs Gain
AFE5816 D032_SBAS641.gif
Across gain codes
Figure 31. AVDD_3P15 Power-Supply Modulation Ratio vs
100-mVPP Supply Noise Frequencies
AFE5816 D034_SBAS641.gif
Across gain codes
Figure 33. AVDD_3P15 Power-Supply Rejection Ratio vs
100-mVPP Supply Noise Frequencies
AFE5816 D037_SBAS641.gif
Figure 35. Output and Gain Code Step Response vs Time
AFE5816 D040_SBAS641.gif
For the input in Figure 36, gain = 21 dB, across positive and negative overload
Figure 37. Device Pulse Inversion Output vs Time
AFE5816 D042_SBAS641.gif
VIN = large amplitude (50 mVPP)
followed by small amplitude (500 µVPP)
Figure 39. Output Code Overload Recovery vs Time
AFE5816 D044_SBAS641.gif
Across digital HPF corner settings
Figure 41. Digital High-Pass Filter Gain Response vs Frequency
AFE5816 D060_SBAS641.gif
Across power modes
Figure 43. VCA Power vs Gain Code
AFE5816 D063_SBAS641.gif
Across power modes
Figure 45. AVDD_1P9 Supply Current vs Gain Code
AFE5816 D058_SBAS641.gif
12-bit resolution
Figure 47. AVDD_1P8, DVDD_1P8 and DVDD_1P2 Supply Current vs ADC Sample Rate
AFE5816 D059_SBAS641.gif
14-bit resolution
Figure 48. AVDD_1P8, DVDD_1P8 and DVDD_1P2 Supply Current vs ADC Sample Rate
AFE5816 D064_SBAS641.gif
For all power modes
Figure 49. Total Power Dissipation vs ADC Sample Rate

Typical Characteristics: CW Mode

At TA = 25°C, unless otherwise noted. Supply: AVDD_1P8 = 1.8 V, AVDD_1P9 = 1.9 V, AVDD_3P15 = 3.15 V, DVDD_1P2 = 1.2 V, and DVDD_1P8 = 1.8 V. Input to the device: input signal = 2 MHz, CW_CLK1X = 2-MHz differential, and CW_CLK_NX = 32-MHz differential. Device settings: CW clock mode = 16X, and 1X and 16X clock buffer in differential mode, and ADC in power-down mode. Minimum and maximum values are specified across the full temperature range.
AFE5816 D011_SBAS641.gif
Across LNA HPF corner settings
Figure 50. Full-Channel, Low-Frequency Amplitude Response vs Frequency
AFE5816 D014_SBAS641.gif
fIN = 2 MHz, across one channel and 16 channels
Figure 52. CW Phase Noise vs Frequency
AFE5816 D067_SBAS641.gif
Across all CW clock modes
Figure 54. AVDD_1P9 and AVDD_3P15 Supply Current vs CW Clock Frequency
AFE5816 D013_SBAS641.gif
fIN = 2 MHz, one channel across CW clock modes
Figure 51. CW Phase Noise vs Frequency
AFE5816 D015_SBAS641.gif
fIN = 2 MHz, 16 channels across CW clock modes
Figure 53. CW Phase Noise vs Frequency
AFE5816 D068_SBAS641.gif
Figure 55. Power vs CW 1X Clock Frequency