SLASEQ7E May   2018  – March 2019 AFE7681 , AFE7683 , AFE7684 , AFE7685 , AFE7686


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
  4. 4Device and Documentation Support
    1. 4.1 Device Support
      1. 4.1.1 Third-Party Products Disclaimer
    2. 4.2 Documentation Support
      1. 4.2.1 Related Documentation
    3. 4.3 Related Links
    4. 4.4 Community Resources
    5. 4.5 Trademarks
    6. 4.6 Electrostatic Discharge Caution
    7. 4.7 Export Control Notice
    8. 4.8 Glossary
  5. 5Mechanical, Packaging, and Orderable Information
    1. 5.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital Pre-Distortion) of the Power Amplifier (PA) on the transmitter path.

The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector and various digital power detectors to assist AGC control for receiver channels, and two RF overload detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as 4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by allowing use of a lower frequency reference clock.

Device Information(1)

AFE7685 FC-BGA 17.00 mm x 17.00 mm
AFE7686 FC-BGA 17.00 mm x 17.00 mm
AFE7684 FC-BGA 17.00 mm x 17.00 mm
AFE7683 FC-BGA 17.00 mm x 17.00 mm
AFE7681 FC-BGA 17.00 mm x 17.00 mm
For all available packages, see the orderable addendum at the end of the data sheet.