SBASA21A December   2021  – September 2022 AFE8030

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4 AFE8030 Functional Block Diagram
  5. 5Revision History
  6. 6Device and Documentation Support
    1. 6.1 Device Support
    2. 6.2 Receiving Notification of Documentation Updates
    3. 6.3 Support Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Glossary
  7. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Octal RF sampling 12-GSPS transmit DACs
  • Octal RF sampling 4-GSPS receive ADCs
  • Dual RF sampling 4-GSPS feedback ADCs
  • Maximum RF signal bandwidth:
    • TX/FB: 800 MHz.
      • 1200 MHz in 4-channel mode
    • RX: 400 MHz
      • 800 MHz in 4-channel mode
  • RF frequency range: up to 6GHz
  • Digital Step Attenuators (DSA):
    • TX: 40-dB range, 1-dB analog and 0.125-dB digital steps
    • RX/FB: 31/25-dB range, 1-dB step
  • Single or dual-band DUC/DDCs
  • Dual NCO’s per chain for fast frequency switching
  • Supports TDD operation with fast switching between TX and RX
  • Internal PLL/VCO to generate DAC/ADC clocks
  • Optional external CLK at DAC or ADC rate
  • SerDes data interface:
    • JESD204B and JESD204C
    • 8 SerDes transceivers up to 32.5 Gbps
    • 8b/10b and 64b/66b Encoding
    • 12-bit, 16-bit, 24-bit and 32-bit resolution
    • Subclass 1 multi-device synchronization
  • Package:
    • 17-mm × 17-mm FCBGA, 0.8-mm pitch