SPRSP65B April   2021  – July 2021 AM2431 , AM2432 , AM2434

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagram
      1. 6.1.1 AM243x ALV Pin Diagram
      2. 6.1.2 AM243x ALX Pin Diagram
    2. 6.2 Pin Attributes (ALV Package)
    3. 6.3 Pin Attributes (ALX Package)
    4. 6.4 Signal Descriptions
      1. 6.4.1  ADC
        1.       MAIN Domain Instances
        2. 6.4.1.1 ADC0 Signal Descriptions
      2. 6.4.2  DDRSS
        1.       MAIN Domain Instances
        2. 6.4.2.1 DDRSS0 Signal Descriptions
      3. 6.4.3  GPIO
        1.       MAIN Domain Instances
        2. 6.4.3.1 GPIO0 Signal Descriptions
        3. 6.4.3.2 GPIO1 Signal Descriptions
        4.       MCU Domain Instances
        5. 6.4.3.3 MCU_GPIO0 Signal Descriptions
      4. 6.4.4  I2C
        1.       MAIN Domain Instances
        2. 6.4.4.1 I2C0 Signal Descriptions
        3. 6.4.4.2 I2C1 Signal Descriptions
        4. 6.4.4.3 I2C2 Signal Descriptions
        5. 6.4.4.4 I2C3 Signal Descriptions
        6.       MCU Domain Instances
        7. 6.4.4.5 MCU_I2C0 Signal Descriptions
        8. 6.4.4.6 MCU_I2C1 Signal Descriptions
      5. 6.4.5  MCAN
        1.       MAIN Domain Instances
        2. 6.4.5.1 MCAN0 Signal Descriptions
        3. 6.4.5.2 MCAN1 Signal Descriptions
      6. 6.4.6  SPI (MCSPI)
        1.       MAIN Domain Instances
        2. 6.4.6.1 MCSPI0 Signal Descriptions
        3. 6.4.6.2 MCSPI1 Signal Descriptions
        4. 6.4.6.3 MCSPI2 Signal Descriptions
        5. 6.4.6.4 MCSPI3 Signal Descriptions
        6. 6.4.6.5 MCSPI4 Signal Descriptions
        7.       MCU Domain Instances
        8. 6.4.6.6 MCU_MCSPI0 Signal Descriptions
        9. 6.4.6.7 MCU_MCSPI1 Signal Descriptions
      7. 6.4.7  UART
        1.       MAIN Domain Instances
        2. 6.4.7.1 UART0 Signal Descriptions
        3. 6.4.7.2 UART1 Signal Descriptions
        4. 6.4.7.3 UART2 Signal Descriptions
        5. 6.4.7.4 UART3 Signal Descriptions
        6. 6.4.7.5 UART4 Signal Descriptions
        7. 6.4.7.6 UART5 Signal Descriptions
        8. 6.4.7.7 UART6 Signal Descriptions
        9.       MCU Domain Instances
        10. 6.4.7.8 MCU_UART0 Signal Descriptions
        11. 6.4.7.9 MCU_UART1 Signal Descriptions
      8. 6.4.8  MDIO
        1.       MAIN Domain Instances
        2. 6.4.8.1 MDIO0 Signal Descriptions
      9. 6.4.9  CPSW
        1.       MAIN Domain Instances
        2. 6.4.9.1 CPSW3G0 Signal Descriptions
      10. 6.4.10 ECAP
        1.       MAIN Domain Instances
        2. 6.4.10.1 ECAP0 Signal Descriptions
        3. 6.4.10.2 ECAP1 Signal Descriptions
        4. 6.4.10.3 ECAP2 Signal Descriptions
      11.      EQEP
        1.       MAIN Domain Instances
        2. 6.4.11.1 EQEP0 Signal Descriptions
        3. 6.4.11.2 EQEP1 Signal Descriptions
        4. 6.4.11.3 EQEP2 Signal Descriptions
      12. 6.4.11 EPWM
        1.       MAIN Domain Instances
        2. 6.4.11.1  EPWM Signal Descriptions
        3. 6.4.11.2  EPWM0 Signal Descriptions
        4. 6.4.11.3  EPWM1 Signal Descriptions
        5. 6.4.11.4  EPWM2 Signal Descriptions
        6. 6.4.11.5  EPWM3 Signal Descriptions
        7. 6.4.11.6  EPWM4 Signal Descriptions
        8. 6.4.11.7  EPWM5 Signal Descriptions
        9. 6.4.11.8  EPWM6 Signal Descriptions
        10. 6.4.11.9  EPWM7 Signal Descriptions
        11. 6.4.11.10 EPWM8 Signal Descriptions
      13. 6.4.12 SERDES
        1.       MAIN Domain Instances
        2. 6.4.12.1 SERDES0 Signal Descriptions
      14. 6.4.13 USB
        1.       MAIN Domain Instances
        2. 6.4.13.1 USB0 Signal Descriptions
      15. 6.4.14 OSPI
        1.       MAIN Domain Instances
        2. 6.4.14.1 OSPI0 Signal Descriptions
      16. 6.4.15 GPMC
        1.       MAIN Domain Instances
        2. 6.4.15.1 GPMC0 Signal Descriptions
      17. 6.4.16 MMC
        1.       MAIN Domain Instances
        2. 6.4.16.1 MMC0 Signal Descriptions
        3. 6.4.16.2 MMC1 Signal Descriptions
      18. 6.4.17 FSITX
        1.       MAIN Domain Instances
        2. 6.4.17.1 FSI0 TX Signal Descriptions
        3. 6.4.17.2 FSI1 TX Signal Descriptions
      19. 6.4.18 FSIRX
        1.       MAIN Domain Instances
        2. 6.4.18.1 FSI0 RX Signal Descriptions
        3. 6.4.18.2 FSI1 RX Signal Descriptions
        4. 6.4.18.3 FSI2 RX Signal Descriptions
        5. 6.4.18.4 FSI3 RX Signal Descriptions
        6. 6.4.18.5 FSI4 RX Signal Descriptions
        7. 6.4.18.6 FSI5 RX Signal Descriptions
      20. 6.4.19 CPTS
        1.       MAIN Domain Instances
        2. 6.4.19.1 CPTS0 Signal Descriptions
        3. 6.4.19.2 CP GEMAC CPTS0 Signal Descriptions
      21. 6.4.20 ICSSG
        1.       MAIN Domain Instances
        2. 6.4.20.1 PRU_ICSSG0 Signal Descriptions
        3. 6.4.20.2 PRU_ICSSG1 Signal Descriptions
      22. 6.4.21 DMTIMER
        1.       MAIN Domain Instances
        2. 6.4.21.1 DMTIMER Signal Descriptions
        3.       MCU Domain Instances
        4. 6.4.21.2 MCU_DMTIMER Signal Descriptions
      23. 6.4.22 TRACE
        1.       MAIN Domain Instances
        2. 6.4.22.1 Trace Signal Descriptions
      24. 6.4.23 JTAG
        1.       MAIN Domain Instances
        2. 6.4.23.1 JTAG Signal Descriptions
      25. 6.4.24 SYSBOOT
        1.       MAIN Domain Instances
        2. 6.4.24.1 Sysboot Signal Descriptions
      26. 6.4.25 SYSTEM
        1.       MAIN Domain Instances
        2. 6.4.25.1 System Signal Descriptions
        3.       MCU Domain Instances
        4. 6.4.25.2 MCU System Signal Descriptions
      27. 6.4.26 CLOCK
        1.       MCU Domain Instances
        2. 6.4.26.1 MCU Clock Signal Descriptions
      28. 6.4.27 VMON
        1. 6.4.27.1 VMON Signal Description
      29. 6.4.28 Power Supply
        1. 6.4.28.1 Power Supply Signal Description
    5. 6.5 Pin Multiplexing
    6. 6.6 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1 Fail-Safe Reset (FS RESET) Electrical Characteristics
      2. 7.7.2 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      3. 7.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 7.7.4 eMMCPHY Electrical Characteristics
      5. 7.7.5 SDIO Electrical Characteristics
      6. 7.7.6 ADC12B Electrical Characteristics
      7. 7.7.7 LVCMOS Electrical Characteristics
      8. 7.7.8 USB2PHY Electrical Characteristics
      9. 7.7.9 DDR Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Power-Up Sequencing
        3. 7.10.2.3 Power-Down Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input Clocks / Oscillators
          1. 7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
      5. 7.10.5 Peripherals
        1. 7.10.5.1  CPSW3G
          1. 7.10.5.1.1 CPSW3G MDIO Timing
          2. 7.10.5.1.2 CPSW3G RMII Timing
          3. 7.10.5.1.3 CPSW3G RGMII Timing
        2. 7.10.5.2  DDRSS
        3. 7.10.5.3  ECAP
        4. 7.10.5.4  EPWM
        5. 7.10.5.5  EQEP
        6. 7.10.5.6  FSI
        7. 7.10.5.7  GPIO
        8. 7.10.5.8  GPMC
          1. 7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 7.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 7.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
        9. 7.10.5.9  I2C
          1. 7.10.5.9.1 Timing Requirements for I2C Input Timings
        10. 7.10.5.10 MCAN
        11. 7.10.5.11 MCSPI
          1. 7.10.5.11.1 MCSPI — Master Mode
          2. 7.10.5.11.2 MCSPI — Slave Mode
        12. 7.10.5.12 MMCSD
          1. 7.10.5.12.1 MMC0 - eMMC Interface
            1. 7.10.5.12.1.1 Legacy SDR Mode
            2. 7.10.5.12.1.2 High Speed SDR Mode
            3. 7.10.5.12.1.3 High Speed DDR Mode
            4. 7.10.5.12.1.4 HS200 Mode
          2. 7.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 7.10.5.12.2.1 Default Speed Mode
            2. 7.10.5.12.2.2 High Speed Mode
            3. 7.10.5.12.2.3 UHS–I SDR12 Mode
            4. 7.10.5.12.2.4 UHS–I SDR25 Mode
            5. 7.10.5.12.2.5 UHS–I SDR50 Mode
            6. 7.10.5.12.2.6 UHS–I DDR50 Mode
            7. 7.10.5.12.2.7 UHS–I SDR104 Mode
        13. 7.10.5.13 CPTS
        14. 7.10.5.14 OSPI
          1. 7.10.5.14.1 OSPI With Data Training
            1. 7.10.5.14.1.1 OSPI Switching Characteristics – Data Training
          2. 7.10.5.14.2 OSPI Without Data Training
            1. 7.10.5.14.2.1 OSPI SDR Timing
            2. 7.10.5.14.2.2 OSPI DDR Timing
        15. 7.10.5.15 PCIe
        16. 7.10.5.16 PRU_ICSSG
          1. 7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 7.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 7.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 7.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 7.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 7.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 7.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 7.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 7.10.5.17 Timers
        18. 7.10.5.18 UART
        19. 7.10.5.19 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-R5F Subsystem (R5FSS)
      2. 8.2.2 Arm Cortex-M4F (M4FSS)
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 8.4 Other Subsystems
      1. 8.4.1 PDMA Controller
      2. 8.4.2 Peripherals
        1. 8.4.2.1  ADC
        2. 8.4.2.2  DCC
        3. 8.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 8.4.2.4  ECAP
        5. 8.4.2.5  EPWM
        6. 8.4.2.6  ELM
        7. 8.4.2.7  ESM
        8. 8.4.2.8  GPIO
        9. 8.4.2.9  EQEP
        10. 8.4.2.10 GPMC
        11. 8.4.2.11 I2C
        12. 8.4.2.12 MCAN
        13. 8.4.2.13 MCRC Controller
        14. 8.4.2.14 MCSPI
        15. 8.4.2.15 MMCSD
        16. 8.4.2.16 OSPI
        17. 8.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 8.4.2.18 Serializer/Deserializer (SerDes)
        19. 8.4.2.19 RTI
        20. 8.4.2.20 DMTIMER
        21. 8.4.2.21 UART
        22. 8.4.2.22 Universal Serial Bus Subsystem(USBSS)
  9. Applications, Implementation, and Layout
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Unused Pins
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 General Routing Guidelines
      2. 9.3.2 DDR Board Design and Layout Guidelines
      3. 9.3.3 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.3.1 No Loopback and Internal Pad Loopback
        2. 9.3.3.2 External Board Loopback
        3. 9.3.3.3 DQS (only available in Octal Flash devices)
      4. 9.3.4 USB VBUS Design Guidelines
      5. 9.3.5 System Power Supply Monitor Design Guidelines
      6. 9.3.6 High Speed Differential Signal Routing Guidance
      7. 9.3.7 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
  • ALX|293
Thermal pad, mechanical data (Package|Pins)
Orderable Information

GPMC0 Signal Descriptions

Table 6-53 GPMC0 Signal Descriptions
SIGNAL
NAME
SIGNAL
TYPE
DESCRIPTIONALVALX
GPMC0_ADVn_ALEOGPMC Address Valid (active low) or Address Latch EnableP16
GPMC0_CLKOGPMC clockR17
GPMC0_DIROGPMC Data Bus Signal Direction ControlN17
GPMC0_OEn_REnOGPMC Output Enable (active low) or Read Enable (active low)R18
GPMC0_WEnOGPMC Write Enable (active low)T21
GPMC0_WPnOGPMC Flash Write Protect (active low)N16
GPMC0_A0OZGPMC Address 0 Output. Only used to effectively address 8-bit data non-multiplexed memoriesU2, U7G1, T2
GPMC0_A1OZGPMC address 1 Output in A/D non-multiplexed mode and Address 17 in A/D multiplexed modeAA2, V7K2, Y4
GPMC0_A2OZGPMC address 2 Output in A/D non-multiplexed mode and Address 18 in A/D multiplexed modeT2, W7H5, U3
GPMC0_A3OZGPMC address 3 Output in A/D non-multiplexed mode and Address 19 in A/D multiplexed modeV4, W11AA10, N2
GPMC0_A4OZGPMC address 4 Output in A/D non-multiplexed mode and Address 20 in A/D multiplexed modeU4, V11N3, Y10
GPMC0_A5OZGPMC address 5 Output in A/D non-multiplexed mode and Address 21 in A/D multiplexed modeAA12, V1K4, Y11
GPMC0_A6OZGPMC address 6 Output in A/D non-multiplexed mode and Address 22 in A/D multiplexed modeW1, Y12G2, V12
GPMC0_A7OZGPMC address 7 Output in A/D non-multiplexed mode and Address 23 in A/D multiplexed modeW12, Y4P2, Y12
GPMC0_A8OZGPMC address 8 Output in A/D non-multiplexed mode and Address 24 in A/D multiplexed modeAA13, T6AA11, T4
GPMC0_A9OZGPMC address 9 Output in A/D non-multiplexed mode and Address 25 in A/D multiplexed modeU11, U6R5, V10
GPMC0_A10OZGPMC address 10 Output in A/D non-multiplexed mode and Address 26 in A/D multiplexed modeU5, V15M4, Y14
GPMC0_A11OZGPMC address 11 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeAA4, U12T3, W11
GPMC0_A12OZGPMC address 12 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeP2, V14E4, Y16
GPMC0_A13OZGPMC address 13 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeP3, W14D2, U13
GPMC0_A14OZGPMC address 14 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeAA10, AA3K1, Y6
GPMC0_A15OZGPMC address 15 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeR6, V10AA8, N1
GPMC0_A16OZGPMC address 16 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeT5, U10N4, Y9
GPMC0_A17OZGPMC address 17 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeAA11, U1E1, W9
GPMC0_A18OZGPMC address 18 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeT4, Y11L2, V9
GPMC0_A19OZGPMC address 19 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeR5, Y10F5, Y8
GPMC0_A20OZGPMC address 20 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeR21
GPMC0_A21OZGPMC address 21 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeY18
GPMC0_A22OZGPMC address 22 Output in A/D non-multiplexed mode and unused in A/D multiplexed modeN16
GPMC0_AD0IOGPMC Data 0 Input/Output in A/D non-multiplexed mode and additionally Address 1 Output in A/D multiplexed modeT20R21
GPMC0_AD1IOGPMC Data 1 Input/Output in A/D non-multiplexed mode and additionally Address 2 Output in A/D multiplexed modeU21R20
GPMC0_AD2IOGPMC Data 2 Input/Output in A/D non-multiplexed mode and additionally Address 3 Output in A/D multiplexed modeT18T19
GPMC0_AD3IOGPMC Data 3 Input/Output in A/D non-multiplexed mode and additionally Address 4 Output in A/D multiplexed modeU20V21
GPMC0_AD4IOGPMC Data 4 Input/Output in A/D non-multiplexed mode and additionally Address 5 Output in A/D multiplexed modeU18U21
GPMC0_AD5IOGPMC Data 5 Input/Output in A/D non-multiplexed mode and additionally Address 6 Output in A/D multiplexed modeU19T20
GPMC0_AD6IOGPMC Data 6 Input/Output in A/D non-multiplexed mode and additionally Address 7 Output in A/D multiplexed modeV20T18
GPMC0_AD7IOGPMC Data 7 Input/Output in A/D non-multiplexed mode and additionally Address 8 Output in A/D multiplexed modeV21U19
GPMC0_AD8IOGPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed modeV19U18
GPMC0_AD9IOGPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed modeT17U20
GPMC0_AD10IOGPMC Data 10 Input/Output in A/D non-multiplexed mode and additionally Address 11 Output in A/D multiplexed modeR16V20
GPMC0_AD11IOGPMC Data 11 Input/Output in A/D non-multiplexed mode and additionally Address 12 Output in A/D multiplexed modeW20W20
GPMC0_AD12IOGPMC Data 12 Input/Output in A/D non-multiplexed mode and additionally Address 13 Output in A/D multiplexed modeW21Y20
GPMC0_AD13IOGPMC Data 13 Input/Output in A/D non-multiplexed mode and additionally Address 14 Output in A/D multiplexed modeV18Y19
GPMC0_AD14IOGPMC Data 14 Input/Output in A/D non-multiplexed mode and additionally Address 15 Output in A/D multiplexed modeY21Y18
GPMC0_AD15IOGPMC Data 15 Input/Output in A/D non-multiplexed mode and additionally Address 16 Output in A/D multiplexed modeY20AA19
GPMC0_AD16IOGPMC Data 16 Input/Output in A/D non-multiplexed mode and additionally Address 17 Output in A/D multiplexed modeY7V4
GPMC0_AD17IOGPMC Data 17 Input/Output in A/D non-multiplexed mode and additionally Address 18 Output in A/D multiplexed modeU8W5
GPMC0_AD18IOGPMC Data 18 Input/Output in A/D non-multiplexed mode and additionally Address 19 Output in A/D multiplexed modeW8AA4
GPMC0_AD19IOGPMC Data 19 Input/Output in A/D non-multiplexed mode and additionally Address 20 Output in A/D multiplexed modeV8Y5
GPMC0_AD20IOGPMC Data 20 Input/Output in A/D non-multiplexed mode and additionally Address 21 Output in A/D multiplexed modeY8AA5
GPMC0_AD21IOGPMC Data 21 Input/Output in A/D non-multiplexed mode and additionally Address 22 Output in A/D multiplexed modeV13U14
GPMC0_AD22IOGPMC Data 22 Input/Output in A/D non-multiplexed mode and additionally Address 23 Output in A/D multiplexed modeAA7Y2
GPMC0_AD23IOGPMC Data 23 Input/Output in A/D non-multiplexed mode and additionally Address 24 Output in A/D multiplexed modeU13V13
GPMC0_AD24IOGPMC Data 24 Input/Output in A/D non-multiplexed mode and additionally Address 25 Output in A/D multiplexed modeW13Y13
GPMC0_AD25IOGPMC Data 25 Input/Output in A/D non-multiplexed mode and additionally Address 26 Output in A/D multiplexed modeU15W16
GPMC0_AD26IOGPMC Data 26 Input/Output in A/D non-multiplexed mode and additionally Address 27 Output in A/D multiplexed modeU14W13
GPMC0_AD27IOGPMC Data 27 Input/Output in A/D non-multiplexed mode and additionally Address 28 Output in A/D multiplexed modeAA8V5
GPMC0_AD28IOGPMC Data 28 Input/Output in A/D non-multiplexed mode and additionally Address 29 Output in A/D multiplexed modeU9W2
GPMC0_AD29IOGPMC Data 29 Input/Output in A/D non-multiplexed mode and additionally Address 30 Output in A/D multiplexed modeW9V6
GPMC0_AD30IOGPMC Data 30 Input/Output in A/D non-multiplexed mode and additionally Address 31 Output in A/D multiplexed modeAA9AA7
GPMC0_AD31IOGPMC Data 31 Input/Output in A/D non-multiplexed mode and additionally Address 0 Output in A/D multiplexed modeY9Y7
GPMC0_BE0n_CLEOGPMC Lower-Byte Enable (active low) or Command Latch EnableP17
GPMC0_BE1nOGPMC Upper-Byte Enable (active low)T19P21
GPMC0_BE2nOGPMC Upper-Byte Enable (active low)V9W6
GPMC0_BE3nOGPMC Upper-Byte Enable (active low)AA14AA14
GPMC0_CSn0OGPMC Chip Select 0 (active low)R19
GPMC0_CSn1OGPMC Chip Select 1 (active low)R20
GPMC0_CSn2OGPMC Chip Select 2 (active low)P19
GPMC0_CSn3OGPMC Chip Select 3 (active low)R21
GPMC0_WAIT0IGPMC External Indication of WaitW19
GPMC0_WAIT1IGPMC External Indication of WaitY18