SPRSPA7C September   2024  – July 2025 AM2612 , AM2612-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Package Comparison
    1. 4.1 Device Identification
    2. 4.2 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM261x ZCZ Pin Diagram
      2. 5.1.2 AM261x ZFG Pin Diagram
      3. 5.1.3 AM261x ZEJ Pin Diagram
      4. 5.1.4 AM261x ZNC Pin Diagram
    2. 5.2 Pin Attributes
      1.      16
      2.      17
    3. 5.3 Signal Descriptions
      1.      19
      2. 5.3.1  ADC
        1.       21
        2.       22
        3.       23
        4. 5.3.1.1 ADC-CMPSS Signal Connections
      3. 5.3.2  ADC_CAL
        1.       26
      4. 5.3.3  ADC VREF
        1.       28
      5. 5.3.4  CPSW
        1.       30
        2.       31
        3.       32
        4.       33
        5.       34
        6.       35
        7.       36
      6. 5.3.5  CPTS
        1.       38
      7. 5.3.6  DAC
        1.       40
      8. 5.3.7  EPWM
        1.       42
        2.       43
        3.       44
        4.       45
        5.       46
        6.       47
        7.       48
        8.       49
        9.       50
        10.       51
      9. 5.3.8  EQEP
        1.       53
        2.       54
      10. 5.3.9  FSI
        1.       56
        2.       57
      11. 5.3.10 GPIO
        1.       59
      12. 5.3.11 GPMC0
        1.       61
      13. 5.3.12 I2C
        1.       63
        2.       64
        3.       65
      14. 5.3.13 LIN
        1.       67
        2.       68
        3.       69
      15. 5.3.14 MCAN
        1.       71
        2.       72
      16. 5.3.15 MMC
        1.       74
      17. 5.3.16 OSPI
        1.       76
        2.       77
      18. 5.3.17 Power Supply
        1.       79
      19. 5.3.18 PRU-ICSS
        1.       81
        2.       82
        3.       83
        4.       84
        5.       85
      20. 5.3.19 SDFM
        1.       87
        2.       88
      21. 5.3.20 SPI
        1.       90
        2.       91
        3.       92
        4.       93
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1.        96
        2. 5.3.21.2 Clocking
          1.        98
          2.        99
          3.        100
        3. 5.3.21.3 Emulation and Debug
          1.        102
          2.        103
        4. 5.3.21.4 SYSTEM
          1.        105
        5. 5.3.21.5 VMON
          1.        107
        6. 5.3.21.6 Reserved
          1.        109
        7.       110
          1.        111
      23. 5.3.22 UART
        1.       113
        2.       114
        3.       115
        4.       116
        5.       117
        6.       118
      24. 5.3.23 USB0
        1.       120
      25. 5.3.24 XBAR
        1.       122
        2.       123
    4. 5.4 Pin Connectivity Requirements
      1.      Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Electrostatic Discharge (ESD) Extended Automotive Ratings
    3. 6.3  Electrostatic Discharge (ESD) Industrial Ratings
    4. 6.4  Power-On Hours (POH) Summary
      1. 6.4.1 Automotive Temperature Profile
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
      1. 6.7.1 Power Consumption - Maximum for R5F at 400MHz
      2. 6.7.2 Power Consumption - Maximum for R5F at 500MHz
    8. 6.8  Electrical Characteristics
      1. 6.8.1 Digital and Analog IO Electrical Characteristics
      2. 6.8.2 Analog to Digital Converter Characteristics
        1. 6.8.2.1 Analog-to-Digital Converter (ADC)
        2. 6.8.2.2 ADC Input Model
      3. 6.8.3 Comparator Subsystem A (CMPSSA)
      4. 6.8.4 Digital-to-Analog Converter (DAC)
      5. 6.8.5 Power Management Unit (PMU)
      6. 6.8.6 Safety Comparators
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 VPP Specifications
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 ZCZ Package Thermal Characteristics
      2. 6.10.2 ZFG Package Thermal Characteristics
      3. 6.10.3 ZEJ Package Thermal Characteristics
      4. 6.10.4 ZNC Package Thermal Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Sequencing
        1. 6.11.2.1 Power-On and Reset Sequencing
          1. 6.11.2.1.1 Power Reset Sequence Description
        2. 6.11.2.2 Power-Down Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 System Timing Conditions
        2. 6.11.3.2 Reset Timing
          1. 6.11.3.2.1 PORz Timing Requirements
          2.        166
          3. 6.11.3.2.2 WARMRSTn Switching Characteristics
          4.        168
          5. 6.11.3.2.3 WARMRSTn Timing Requirements
          6.        170
        3. 6.11.3.3 Safety Signal Timing
          1. 6.11.3.3.1 SAFETY_ERRORn Switching Characteristics
          2.        173
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 Crystal Oscillator (XTAL) Parameters
          2. 6.11.4.1.2 External Clock Characteristics
        2. 6.11.4.2 Clock Timing
          1. 6.11.4.2.1 Clock Timing Requirements
          2.        180
          3. 6.11.4.2.2 Clock Switching Characteristics
          4.        182
      5. 6.11.5 Peripherals
        1. 6.11.5.1  3-port Gigabit Ethernet MAC (CPSW)
          1. 6.11.5.1.1 CPSW MDIO Timing
            1. 6.11.5.1.1.1 CPSW MDIO Timing Conditions
            2. 6.11.5.1.1.2 CPSW MDIO Timing Requirements
            3. 6.11.5.1.1.3 CPSW MDIO Switching Characteristics
            4.         189
          2. 6.11.5.1.2 CPSW RGMII Timing
            1. 6.11.5.1.2.1 CPSW RGMII Timing Conditions
            2. 6.11.5.1.2.2 CPSW RGMII[x]_RCLK Timing Requirements - RGMII Mode
            3. 6.11.5.1.2.3 CPSW RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements
            4.         194
            5. 6.11.5.1.2.4 CPSW RGMII[x]_TCLK Switching Characteristics - RGMII Mode
            6. 6.11.5.1.2.5 CPSW RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
            7.         197
          3. 6.11.5.1.3 CPSW RMII Timing
            1. 6.11.5.1.3.1 CPSW RMII Timing Conditions
            2. 6.11.5.1.3.2 CPSW RMII[x]_REFCLK Timing Requirements - RMII Mode
            3.         201
            4. 6.11.5.1.3.3 CPSW RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
            5.         203
            6. 6.11.5.1.3.4 CPSW RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
            7.         205
        2. 6.11.5.2  Enhanced Capture (eCAP)
          1. 6.11.5.2.1 ECAP Timing Conditions
          2. 6.11.5.2.2 ECAP Timing Requirements
          3.        209
          4. 6.11.5.2.3 ECAP Switching Characteristics
          5.        211
        3. 6.11.5.3  Enhanced Pulse Width Modulation (ePWM)
          1. 6.11.5.3.1 EPWM Timing Conditions
          2. 6.11.5.3.2 EPWM Timing Requirements
          3.        215
          4. 6.11.5.3.3 EPWM Switching Characteristics
          5.        217
          6.        EPWM Characteristics
        4. 6.11.5.4  Enhanced Quadrature Encoder Pulse (eQEP)
          1. 6.11.5.4.1 EQEP Timing Conditions
          2. 6.11.5.4.2 EQEP Timing Requirements
          3.        222
          4. 6.11.5.4.3 EQEP Switching Characteristics
        5. 6.11.5.5  Fast Serial Interface (FSI)
          1. 6.11.5.5.1 FSI Timing Conditions
          2. 6.11.5.5.2 FSIRX Timing Requirements
          3.        227
          4. 6.11.5.5.3 FSIRX Switching Characteristics
          5. 6.11.5.5.4 FSITX Switching Characteristics
          6.        230
          7. 6.11.5.5.5 FSITX SPI Signaling Mode Switching Characteristics
          8.        232
        6. 6.11.5.6  General Purpose Input/Output (GPIO)
          1. 6.11.5.6.1 GPIO Timing Conditions
          2. 6.11.5.6.2 GPIO Timing Requirements
          3. 6.11.5.6.3 GPIO Switching Characteristics
        7. 6.11.5.7  General Purpose Memory Controller (GPMC)
          1. 6.11.5.7.1 GPMC Timing Conditions
          2. 6.11.5.7.2 GPMC/NOR Flash Timing Requirements - Synchronous Mode 100MHz
          3. 6.11.5.7.3 GPMC/NOR Flash Switching Characteristics - Synchronous Mode 100MHz
          4.        241
          5. 6.11.5.7.4 GPMC/NOR Flash Timing Requirements - Asynchronous Mode 100MHz
          6. 6.11.5.7.5 GPMC/NOR Flash Switching Characteristics - Asynchronous Mode 100MHz
          7.        244
          8. 6.11.5.7.6 GPMC/NAND Flash Timing Requirements - Asynchronous Mode 100MHz
          9. 6.11.5.7.7 GPMC/NAND Flash Switching Characteristics - Asynchronous Mode 100MHz
          10.        247
        8. 6.11.5.8  Inter-Integrated Circuit (I2C)
          1. 6.11.5.8.1 I2C
        9. 6.11.5.9  Local Interconnect Network (LIN)
          1. 6.11.5.9.1 LIN Timing Conditions
          2. 6.11.5.9.2 LIN Timing Requirements
          3. 6.11.5.9.3 LIN Switching Characteristics
        10. 6.11.5.10 Modular Controller Area Network (MCAN)
          1. 6.11.5.10.1 MCAN Timing Conditions
          2. 6.11.5.10.2 MCAN Switching Characteristics
        11. 6.11.5.11 Serial Peripheral Interface (SPI)
          1. 6.11.5.11.1 SPI Timing Conditions
          2. 6.11.5.11.2 SPI Controller Mode Timing Requirements
          3.        260
          4. 6.11.5.11.3 SPI Controller Mode Switching Characteristics (Clock Phase = 0)
          5.        262
          6. 6.11.5.11.4 SPI Peripheral Mode Timing Requirements
          7.        264
          8. 6.11.5.11.5 SPI Peripheral Mode Switching Characteristics
          9.        266
        12. 6.11.5.12 Multi-Media Card/Secure Digital (MMCSD)
          1. 6.11.5.12.1 MMC Timing Conditions
          2. 6.11.5.12.2 MMC Timing Requirements - SD Card Default Speed Mode
          3.        270
          4. 6.11.5.12.3 MMC Switching Characteristics - SD Card Default Speed Mode
          5.        272
          6. 6.11.5.12.4 MMC Timing Requirements - SD Card High Speed Mode
          7.        274
          8. 6.11.5.12.5 MMC Switching Characteristics - SD Card High Speed Mode
          9.        276
        13. 6.11.5.13 Octal Serial Peripheral Interface (OSPI)
          1. 6.11.5.13.1 OSPI Timing Conditions
          2. 6.11.5.13.2 OSPI PHY Mode
            1. 6.11.5.13.2.1 OSPI With PHY Data Training
              1. 6.11.5.13.2.1.1 OSPI DLL Delay Mapping for PHY Data Training
              2. 6.11.5.13.2.1.2 OSPI Timing Requirements - PHY Data Training
              3.          283
              4. 6.11.5.13.2.1.3 OSPI Switching Characteristics - PHY Data Training
              5.          285
            2. 6.11.5.13.2.2 OSPI0 Without Data Training
              1. 6.11.5.13.2.2.1 OSPI0 PHY SDR Timing
                1. 6.11.5.13.2.2.1.1 OSPI0 DLL Delay Mapping for PHY SDR Timing Modes
                2. 6.11.5.13.2.2.1.2 OSPI0 Timing Requirements - PHY SDR Mode
                3.           290
                4. 6.11.5.13.2.2.1.3 OSPI0 Switching Characteristics - PHY SDR Mode
                5.           292
              2. 6.11.5.13.2.2.2 OSPI0 PHY DDR Timing
                1. 6.11.5.13.2.2.2.1 OSPI0 DLL Delay Mapping for PHY DDR Timing Modes
                2. 6.11.5.13.2.2.2.2 OSPI0 Timing Requirements - PHY DDR Mode
                3.           296
                4. 6.11.5.13.2.2.2.3 OSPI0 Switching Characteristics - PHY DDR Mode
                5.           298
            3. 6.11.5.13.2.3 OSPI1 Without Data Training
              1. 6.11.5.13.2.3.1 OSPI1 PHY SDR Timing
                1. 6.11.5.13.2.3.1.1 OSPI1 DLL Delay Mapping for PHY SDR Timing Modes
                2. 6.11.5.13.2.3.1.2 OSPI1 Timing Requirements - PHY SDR Mode
                3.           303
                4. 6.11.5.13.2.3.1.3 OSPI1 Switching Characteristics - PHY SDR Mode
                5.           305
              2. 6.11.5.13.2.3.2 OSPI1 PHY DDR Timing
                1. 6.11.5.13.2.3.2.1 OSPI1 DLL Delay Mapping for PHY DDR Timing Modes
                2. 6.11.5.13.2.3.2.2 OSPI1 Timing Requirements - PHY DDR Mode
                3.           309
                4. 6.11.5.13.2.3.2.3 OSPI1 Switching Characteristics - PHY DDR Mode
                5.           311
          3. 6.11.5.13.3 OSPI Tap Mode
            1. 6.11.5.13.3.1 OSPI Tap SDR Timing
              1. 6.11.5.13.3.1.1 OSPI Timing Requirements - Tap SDR Mode
              2.          315
              3. 6.11.5.13.3.1.2 OSPI Switching Characteristics - Tap SDR Mode
              4.          317
            2. 6.11.5.13.3.2 OSPI0 Tap DDR Timing
              1. 6.11.5.13.3.2.1 OSPI Timing Requirements - Tap DDR Mode
              2.          320
              3. 6.11.5.13.3.2.2 OSPI Switching Characteristics - Tap DDR Mode
              4.          322
        14. 6.11.5.14 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
          1. 6.11.5.14.1 PRU-ICSS Programmable Real-Time Unit (PRU)
            1. 6.11.5.14.1.1 PRU-ICSS PRU Timing Conditions
            2. 6.11.5.14.1.2 PRU-ICSS PRU Switching Characteristics - Direct Output Mode
            3.         327
            4. 6.11.5.14.1.3 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            5.         329
            6. 6.11.5.14.1.4 PRU-ICSS PRU Timing Requirements - Shift In Mode
            7.         331
            8. 6.11.5.14.1.5 PRU-ICSS PRU Switching Characteristics - Shift Out Mode
            9.         333
          2. 6.11.5.14.2 PRU-ICSS PRU Sigma Delta and Peripheral Interface
            1. 6.11.5.14.2.1 PRU-ICSS PRU Sigma Delta and Peripheral Interface Timing Conditions
            2. 6.11.5.14.2.2 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            3.         337
            4. 6.11.5.14.2.3 PRU-ICSS PRU Timing Requirements - Peripheral Interface Mode
            5.         339
            6. 6.11.5.14.2.4 PRU-ICSS PRU Switching Characteristics - Peripheral Interface Mode
            7.         341
          3. 6.11.5.14.3 PRU-ICSS Pulse Width Modulation (PWM)
            1. 6.11.5.14.3.1 PRU-ICSS PWM Timing Conditions
            2. 6.11.5.14.3.2 PRU-ICSS PWM Switching Characteristics
            3.         345
          4. 6.11.5.14.4 PRU-ICSS Industrial Ethernet Peripheral (IEP)
            1. 6.11.5.14.4.1 PRU-ICSS IEP Timing Conditions
            2. 6.11.5.14.4.2 PRU-ICSS IEP Timing Requirements - Input Validated with SYNCx
            3.         349
            4. 6.11.5.14.4.3 PRU-ICSS IEP Timing Requirements - Digital IOs
            5.         351
            6. 6.11.5.14.4.4 PRU-ICSS IEP Timing Requirements - LATCHx_IN
            7.         353
          5. 6.11.5.14.5 PRU-ICSS Universal Asynchronous Receiver Transmitter (UART)
            1. 6.11.5.14.5.1 PRU-ICSS UART Timing Conditions
            2. 6.11.5.14.5.2 PRU-ICSS UART Timing Requirements
            3. 6.11.5.14.5.3 PRU-ICSS UART Switching Characteristics
            4.         358
          6. 6.11.5.14.6 PRU-ICSS Enhanced Capture Peripheral (ECAP)
            1. 6.11.5.14.6.1 PRU-ICSS ECAP Timing Conditions
            2. 6.11.5.14.6.2 PRU-ICSS ECAP Timing Requirements
            3.         362
            4. 6.11.5.14.6.3 PRU-ICSS ECAP Switching Characteristics
            5.         364
          7. 6.11.5.14.7 PRU-ICSS MDIO and MII
            1. 6.11.5.14.7.1 PRU-ICSS MDIO Timing
              1. 6.11.5.14.7.1.1 PRU-ICSS MDIO Timing Conditions
              2. 6.11.5.14.7.1.2 PRU-ICSS MDIO Timing Requirements
              3. 6.11.5.14.7.1.3 PRU-ICSS MDIO Switching Characteristics
              4.          370
            2. 6.11.5.14.7.2 PRU-ICSS MII Timing
              1. 6.11.5.14.7.2.1 PRU-ICSS MII Timing Conditions
              2. 6.11.5.14.7.2.2 PRU-ICSS MII Timing Requirements - MII[x]_RX_CLK
              3.          374
              4. 6.11.5.14.7.2.3 PRU-ICSS MII Timing Requirements - MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER
              5.          376
              6. 6.11.5.14.7.2.4 PRU-ICSS MII Switching Characteristics - MII[x]_TX_CLK
              7.          378
              8. 6.11.5.14.7.2.5 PRU-ICSS MII Switching Characteristics - MII[x]_TXD[3:0] and MII[x]_TXEN
              9.          380
        15. 6.11.5.15 Sigma Delta Filter Module (SDFM)
          1. 6.11.5.15.1 SDFM Timing Conditions
          2. 6.11.5.15.2 SDFM Switching Characteristics
        16. 6.11.5.16 Universal Asynchronous Receiver/Transmitter (UART)
          1. 6.11.5.16.1 UART Timing Conditions
          2. 6.11.5.16.2 UART Timing Requirements
          3. 6.11.5.16.3 UART Switching Characteristics
          4.        388
        17. 6.11.5.17 Universal Serial Bus (USB)
      6. 6.11.6 Emulation and Debug
        1. 6.11.6.1 JTAG
          1. 6.11.6.1.1 JTAG Timing Conditions
          2. 6.11.6.1.2 JTAG Timing Requirements
          3. 6.11.6.1.3 JTAG Switching Characteristics
          4.        395
        2. 6.11.6.2 Trace
          1. 6.11.6.2.1 Debug Trace Timing Conditions
          2. 6.11.6.2.2 Debug Trace Switching Characteristics
          3.        399
    12. 6.12 Decoupling Capacitor Requirements
      1. 6.12.1 Decoupling Capacitor Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 External Oscillator
      2. 8.1.2 JTAG, EMU, and TRACE
      3. 8.1.3 Hardware Reference Design and Guidelines
      4. 8.1.4 USB 2.0 Operation
    2. 8.2 OSPI Reset
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
6.11.2.1.1 Power Reset Sequence Description

The following set of steps shall occur on the EVM and AM261x to boot the device from power-on reset.

  1. PORz is held low by the external power supply monitor
  2. VDDSHV_x 3.3V supply ramps to its nominal voltage
    1. This requires a logical AND be applied to the power good signal generated from each supply
  3. Delay at least 50μs after VDDSHV_x 3.3VB is at valid range
  4. VDDSHV_x 1.8V and VDD 1.2V/1.25V supplies ramp to their nominal voltages (no constraint on order of 1.8V and 1.2V/1.25V ramp)
  5. SOP[3:0] pins held in their boot latch state
  6. Power-Good supervisor output triggers based on valid 3.3V, 1.8V, and 1.2V/1.25V all being at valid range
  7. PORz low to high transition is triggered by Power-Good supervisor output
    1. Warm Reset output will toggle low to high tWARMRSTZ seconds after PORz transition
  8. After internal supply monitors show externally and internally generated supplies are stable, the SOP[3:0] pin states are latched
  9. R5F cores are unhalted and SOP selected boot ROM execution begins