SLLS849E april   2008  – august 2023 AM26LV32E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 ±7-V Common-Mode Range With ±200-mV Sensitivity
      2. 8.3.2 Input Fail-Safe Circuitry
      3. 8.3.3 Active-High and Active-Low
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Disable
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  14. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The AM26LV32E device consists of quadruple differential line receivers with 3-state outputs. This device is designed to meet TIA/EIA-422-B and ITU recommendation V.11 drivers with reduced supply voltage. The device is optimized for balanced bus transmission at switching rates up to 32 MHz. The 3-state outputs permit connection directly to a bus-organized system. The AM26LV32E has an internal fail-safe circuitry that prevents the device from putting an unknown voltage signal at the receiver outputs. In the open fail-safe, a high state is produced at the respective output. This device is supported for partial-power-down applications using Ioff. Ioff circuitry disables the outputs, preventing damaging current back-flow through the device when it is powered down.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
AM26LV32E SO (16) 10.2 mm × 7.8 mm
SOIC (16) 9.9 mm x 6 mm
VQFN (16) 4 mm x 3.5 mm
TSSOP (16) 5 mm x 6.4 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
GUID-E367D030-AF94-40A0-85AF-67D36C5325E6-low.gif Logic Diagram (Positive Logic)