5 Specifications

5.1 Absolute Maximum Ratings (Unless Otherwise Noted)(1)(2)

MIN MAX UNIT
Steady State Supply voltage ranges: USB PHYs, 0.9 V (VDD_USB_0P9) -0.3 1.35 V
Core (CVDD, CVDDC, VDDT_SATA, VDDT_PCIE, VDDA_HDMI, VDDA_HD_1P0, VDDA_SD_1P0) -0.3 1.2 V
IO, 1.5 V (VDDA_PLL, VDDR_SATA, VDDR_PCIE, DVDD_DDR0, DVDD_DDR1)(3) -0.3 2.45 V
IO, 1.8 V (DVDD1P8, DEVOSC_DVDD18, VDD_USB0_1P8, VDD_USB1_1P8, VDDA_REF_1P8, VDDA_HD_1P8, VDDA_SD_1P8, DVDD_DDR0, DVDD_DDR1)(3) -0.3 2.45 V
IO, 3.3 V (DVDD_3P3, VDD_USB0_3P3, VDD_USB1_3P3) 0 3.8 V
Input and Output voltage ranges: V IO, 1.5-V pins -0.3
-0.3 		2.45
DVDD_DDRx + 0.3(3)		 V
V IO, 1.8-V pins -0.3
-0.3
-0.3 		2.45
DVDD1P8 + 0.3
DVDD_DDRx + 0.3(3)		 V
V IO, 3.3-V pins
(Steady State)		 -0.3
-0.3 		3.8
DVDD_3P3 + 0.3		 V
V IO, 3.3-V pins
(Transient Overshoot and Undershoot)		 20% of DVDD_3P3 for up to 20% of the signal period V
Operating junction temperature range, TJ:(4) (default) 0 95 °C
extended temperature -40 105
Storage temperature range, Tstg: (Default) -55 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
(3) For supply voltage pins, DVDD_DDRx:
  • 1.5 V is used for DDR3 SDRAM.
  • 1.8 V is used for DDR2 SDRAM.
(4) A heat dissipation solution is required for proper device operation. Thermal performance of the overall system must be carefully considered to ensure conformance with the recommended operating conditions. Heat generated by this device must be removed with the help of heat sinks, heat spreaders, or airflow. SmartReflex can significantly lower the power consumption of this device and its use is required for proper device operation. A thermal model can be provided for thermal simulation to estimate the system thermal environment. Contact your local TI representative for availability.

5.2 ESD Ratings

VALUE UNIT
ESD stress voltage, VESD:(1) HBM (Human Body Model)(2) ±1000 V
CDM (Charged-Device Model)(3) ±250 V
(1) Electrostatic discharge (ESD) to measure device sensitivity or immunity to damage caused by electrostatic discharges into the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
CVDD Supply voltage, Variable Core, Adaptive Voltage Scaling (CVDD)(1) Initial Startup VINITnom × 0.95 1.00 or 1.05(7) VINITnom × 1.05 V
CYGA120 & CYG135 SRnom(8) × 0.95 0.85 - 1.00 SRnom × 1.05
CYG120 SRnom × 0.95 0.85-1.10 SRnom × 1.05
CVDDC Supply voltage, Constant Core (CVDDC, VDDT_SATA, VDDT_PCIE, VDDA_HDMI, VDDA_HD_1P0, VDDA_SD_1P0) 0.95 1 1.05 V
DVDD Supply voltage, IO, 3.3 V (DVDD_3P3, VDD_USB0_3P3, VDD_USB1_3P3)
(except I2C pins)		 3.13 3.3 3.47 V
Supply voltage, IO, I2C (DVDD_3P3) 3.13 3.3 3.47 V
Supply voltage, IO, 1.8 V (DVDD1P8, DEVOSC_DVDD18, VDD_USB0_1P8, VDD_USB1_1P8, VDDA_REF_1P8, VDDA_HD_1P8, VDDA_SD_1P8, DVDD_DDR0, DVDD_DDR1)(2) 1.71 1.8 1.89 V
Supply voltage, IO, 1.5 V (VDDA_PLL, VDDR_SATA, VDDR_PCIE, DVDD_DDR0, DVDD_DDR1)(2) 1.43 1.5 1.58 V
Supply voltage, IO, 0.9 V (VDD_USB_0P9) 0.85 0.9 0.95 V
VSS Supply ground (VSS, VSSA_PLL, VSSA_HD, VSSA_SD, VSSA_REF_1P8, DEVOSC_VSS)(3) 0 0 0 V
DDR_VREF DDR2 and DDR3 reference voltage(4) 0.48DVDD_DDRx 0.5DVDD_DDRx 0.52DVDD_DDRx V
VIH High-level input voltage, 3.3 V (except I2C pins) 2 V
High-level input voltage, I2C 0.7DVDD_3P3
High-level input voltage, 1.8 V 0.65DVDD1P8
VIL Low-level input voltage, 3.3 V (except I2C pins) 0.8 V
Low-level input voltage, I2C 0.3DVDD_3P3
Low-level input voltage, 1.8 V 0.35DVDD1P8
IOH High-level output current 6-mA IO buffers -6 mA
DDR[0], DDR[1] buffers @ 50-Ω impedance setting -8
IOL Low-level output current 6-mA IO buffers 6 mA
DDR[0], DDR[1] buffers @ 50-Ω impedance setting 8
VID Differential input voltage (SERDES_CLKN and SERDES_CLKP), [AC coupled] 0.25 2.0 V
tt Transition time, 10%-90%, All Inputs (unless otherwise specified in the electrical data sections) Lesser of 0.25P or 10(5) ns
TJ Operating junction temperature range(6) 0 95 °C
Extended operating junction temperature range -40 105
(1) This device supports, and requires the use of, SmartReflex technology with Adaptive Voltage Scaling based on die temperature and performance. The SmartReflex codes output from the device correspond to up to 32 linear voltage steps within the specified voltage range (32 steps is the recommended software upper limit and is not constrained by the silicon design), with the option to use fewer steps if desired, with a minimum of eight steps. TI requires that users design a supply that can handle multiple voltage steps within this range with ± 5% tolerances. Not incorporating a flexible supply may limit the system's ability to use the power saving capabilities of the SmartReflex technology. TI recommends using a fault-tolerant power supply design to protect against over-current conditions. For more details about adaptive voltage scaling for this device, see the AVS FAQ. For AVS disable data to aid in design of robust power supplies that may withstand momentary AVS control failure, see the device Power Estimation Spreadsheet (literature number SPRABK3).
(2) For supply voltage pins, DVDD_DDRx:
  • 1.5 V is used for DDR3 SDRAM.
  • 1.8 V is used for DDR2 SDRAM.
(3) Oscillator ground (DEVOSC_VSS) must be kept separate from other grounds and connected directly to the crystal load capacitor ground.
(4) DDR_VREF is expected to equal 0.5DVDD_DDRx of the transmitting device and to track variations in the DVDD_DDRx.
(5) P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input signals.
(6) A heat dissipation solution is required for proper device operation. Thermal performance of the overall system must be carefully considered to ensure conformance with the recommended operating conditions. Heat generated by this device must be removed with the help of heat sinks, heat spreaders, or airflow. SmartReflex can significantly lower the power consumption of this device and its use is required for proper device operation. A thermal model can be provided for thermal simulation to estimate the system thermal environment. Contact your local TI representative for availability.
(7) The initial CVDD voltage at power on must be 1.00V nominal (for CYGA120 and CYG135 devices) or 1.05V nominal (for CYG120 devices) and it must transition to the AVS target value adjusted by a AVS driver. This is required to maintain full power functionality and reliability targets specified by TI.
(8) SRnom refers to the unique SmartReflex core supply voltage set from the factory for each individual device.

Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Temperature (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
VOH Low and full speed: USB_DN and USB_DP 2.8 VDD_USBx_3P3 V
High speed: USB_DN and USB_DP 360 440 mV
High-level output voltage (3.3-V IO) DVDD_3P3 = MIN, IOH = MAX 2.4 V
VOL Low and full speed: USB_DN and USB_DP 0.0 0.3 V
High speed: USB_DN and USB_DP -10 10 mV
Low-level output voltage (3.3-V IO except I2C pins) DVDD_3P3 = MIN, IOL = MAX 0.4 V
Low-level output voltage
(3.3-V IO I2C pins)		 IO = 3 mA 0.4 V
II(2) Input current [DC]
(except I2C pins)		 VI = VSS to DVDD_3P3 without opposing internal resistor ±1 µA
VI = VSS to DVDD_3P3 with opposing internal pullup resistor(3) 100 µA
VI = VSS to DVDD_3P3 with opposing internal pulldown resistor(3) -100 µA
Input current [DC] (I2C) VI = VSS to DVDD_3P3 ±20 µA
IOZ(4) IO Off-state output current VO = DVDD_3P3 or VSS; internal pull disabled ±5 µA
VO = DVDD_3P3 or VSS; internal pull enabled ±100 µA
ICDD
  • Case Temp = 60ºC
  • ARM at 1.2 GHz, 70% utilization
  • HDMI display
  • SGX530 at 150 MHz, 15 fps
  • EMIF0 and EMIF1 at 200 MHz, 1120 MBps
  • USB 1x, EMAC 1x
  • AVS Variable Core voltage = 0.8 V
mA
Constant Core (CVDDC) supply current(5) 1093
Variable Core (CVDD) supply current(5) 4099
IDDD
  • Case Temp = 60ºC
  • ARM at 1.2 GHz, 70% utilization
  • HDMI display
  • SGX530 at 150 MHz, 15 fps
  • EMIF0 and EMIF1 at 200 MHz, 1120 MBps
  • USB 1x, EMAC 1x
  • AVS Variable Core voltage = 0.8 V
mA
3.3-V IO (DVDD_3P3, USB_VDDA3P3) supply current(5) 19
1.8-V IO (DVDD1P8, DVDD_DDRx) supply current(5)(6) 11
1.5-V IO (DVDD_DDRx) supply current(5)(6) 235
CI Input capacitance 2.8 pF
Co Output capacitance 2.8 pF
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II indicates the input leakage current and off-state (Hi-Z) output leakage current.
(3) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(4) IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(5) The actual current draw varies across manufacturing processes and is highly application-dependent. For use-case specific power estimates, see the device Power Estimation Spreadsheet (literature number SPRABK3).
(6) For supply voltage pins, DVDD_DDRx:
  • 1.5 V is used for DDR3 SDRAM.
  • 1.8 V is used for DDR2 SDRAM.

5.4 Thermal Resistance Characteristics

Table 5-1 Thermal Resistance Characteristics (PBGA Package) [CYG]

NO. °C/W(1)
1 RΘJC Junction-to-case 0.21
2 RΘJB Junction-to-board 3.93
(1) For proper device operation, a heatsink is required.