4.3.7 External Memory Interfaces

Table 4-27 DDR Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4]
ddr_a0 DDR SDRAM ROW/COLUMN ADDRESS O N1
ddr_a1 DDR SDRAM ROW/COLUMN ADDRESS O L1
ddr_a2 DDR SDRAM ROW/COLUMN ADDRESS O L2
ddr_a3 DDR SDRAM ROW/COLUMN ADDRESS O P2
ddr_a4 DDR SDRAM ROW/COLUMN ADDRESS O P1
ddr_a5 DDR SDRAM ROW/COLUMN ADDRESS O R5
ddr_a6 DDR SDRAM ROW/COLUMN ADDRESS O R4
ddr_a7 DDR SDRAM ROW/COLUMN ADDRESS O R3
ddr_a8 DDR SDRAM ROW/COLUMN ADDRESS O R2
ddr_a9 DDR SDRAM ROW/COLUMN ADDRESS O R1
ddr_a10 DDR SDRAM ROW/COLUMN ADDRESS O M6
ddr_a11 DDR SDRAM ROW/COLUMN ADDRESS O T5
ddr_a12 DDR SDRAM ROW/COLUMN ADDRESS O T4
ddr_a13 DDR SDRAM ROW/COLUMN ADDRESS O N5
ddr_a14 DDR SDRAM ROW/COLUMN ADDRESS O T3
ddr_a15 DDR SDRAM ROW/COLUMN ADDRESS O T2
ddr_ba0 DDR SDRAM BANK ADDRESS O K1
ddr_ba1 DDR SDRAM BANK ADDRESS O K2
ddr_ba2 DDR SDRAM BANK ADDRESS O K3
ddr_casn DDR SDRAM COLUMN ADDRESS STROBE. (ACTIVE LOW) O N3
ddr_ck DDR SDRAM CLOCK (Differential+) O M2
ddr_cke0 DDR SDRAM CLOCK ENABLE O M3
ddr_cke1 DDR SDRAM CLOCK ENABLE1 O N6
ddr_csn0 DDR SDRAM CHIP SELECT0 O M5
ddr_csn1 DDR SDRAM CHIP SELECT1 O M4
ddr_d0 DDR SDRAM DATA IO E3
ddr_d1 DDR SDRAM DATA IO E2
ddr_d2 DDR SDRAM DATA IO E1
ddr_d3 DDR SDRAM DATA IO F3
ddr_d4 DDR SDRAM DATA IO G4
ddr_d5 DDR SDRAM DATA IO G3
ddr_d6 DDR SDRAM DATA IO G2
ddr_d7 DDR SDRAM DATA IO G1
ddr_d8 DDR SDRAM DATA IO H1
ddr_d9 DDR SDRAM DATA IO J6
ddr_d10 DDR SDRAM DATA IO J5
ddr_d11 DDR SDRAM DATA IO J4
ddr_d12 DDR SDRAM DATA IO J3
ddr_d13 DDR SDRAM DATA IO K6
ddr_d14 DDR SDRAM DATA IO K5
ddr_d15 DDR SDRAM DATA IO K4
ddr_d16 DDR SDRAM DATA IO V5
ddr_d17 DDR SDRAM DATA IO V4
ddr_d18 DDR SDRAM DATA IO V3
ddr_d19 DDR SDRAM DATA IO V2
ddr_d20 DDR SDRAM DATA IO V1
ddr_d21 DDR SDRAM DATA IO W4
ddr_d22 DDR SDRAM DATA IO W5
ddr_d23 DDR SDRAM DATA IO W6
ddr_d24 DDR SDRAM DATA IO Y2
ddr_d25 DDR SDRAM DATA IO Y3
ddr_d26 DDR SDRAM DATA IO Y4
ddr_d27 DDR SDRAM DATA IO AA3
ddr_d28 DDR SDRAM DATA IO AB2
ddr_d29 DDR SDRAM DATA IO AB1
ddr_d30 DDR SDRAM DATA IO AC1
ddr_d31 DDR SDRAM DATA IO AC2
ddr_dqm0 DDR WRITE ENABLE / DATA MASK FOR DATA[7:0] O F4
ddr_dqm1 DDR WRITE ENABLE / DATA MASK FOR DATA[15:8] O H2
ddr_dqm2 DDR WRITE ENABLE / DATA MASK FOR DATA[23:16] O V6
ddr_dqm3 DDR WRITE ENABLE / DATA MASK FOR DATA[31:24] O Y1
ddr_dqs0 DDR DATA STROBE FOR DATA[7:0] (Differential+) IO F2
ddr_dqs1 DDR DATA STROBE FOR DATA[15:8] (Differential+) IO J2
ddr_dqs2 DDR DATA STROBE FOR DATA[23:16] (Differential+) IO W1
ddr_dqs3 DDR DATA STROBE FOR DATA[31:24] (Differential+) IO AA1
ddr_dqsn0 DDR DATA STROBE FOR DATA[7:0] (Differential-) IO F1
ddr_dqsn1 DDR DATA STROBE FOR DATA[15:8] (Differential-) IO J1
ddr_dqsn2 DDR DATA STROBE FOR DATA[23:16] (Differential-) IO W2
ddr_dqsn3 DDR DATA STROBE FOR DATA[31:24] (Differential-) IO AA2
ddr_nck DDR SDRAM CLOCK (Differential-) O M1
ddr_odt0 DDR SDRAM ODT0 O U1
ddr_odt1 DDR SDRAM ODT1 O U2
ddr_rasn DDR SDRAM ROW ADDRESS STROBE (ACTIVE LOW) O N2
ddr_resetn DDR SDRAM RESET (only for DDR3) O T1
ddr_vref Voltage Reference AP (1) T6
ddr_vtp External Resistor for Impedance Training I (2) AC3
ddr_wen DDR SDRAM WRITE ENABLE (ACTIVE LOW) O N4
  1. This terminal is an analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2).
  2. This terminal is an analog passive signal that connects to an external 49.9 ohm 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers.

Table 4-28 General Purpose Memory Controller (GPMC) Signal Descriptions

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZDN [4]
gpmc_a0 GPMC Address O B22, C3
gpmc_a1 GPMC Address O A21, B23, C5
gpmc_a2 GPMC Address O A23, B21, C6
gpmc_a3 GPMC Address O A22, A4, C21
gpmc_a4 GPMC Address O A20, A24, D7
gpmc_a5 GPMC Address O B20, C10, E7
gpmc_a6 GPMC Address O C20, E8
gpmc_a7 GPMC Address O E19, F6
gpmc_a8 GPMC Address O B23, F7
gpmc_a9 GPMC Address O A23, B4
gpmc_a10 GPMC Address O A22, G8
gpmc_a11 GPMC Address O A24, D8
gpmc_a12 GPMC Address O A19
gpmc_a13 GPMC Address O B19
gpmc_a14 GPMC Address O A18
gpmc_a15 GPMC Address O B18
gpmc_a16 GPMC Address O C19, C3
gpmc_a17 GPMC Address O C5, D19
gpmc_a18 GPMC Address O C17, C6
gpmc_a19 GPMC Address O A4, D17
gpmc_a20 GPMC Address O B1, D7
gpmc_a21 GPMC Address O B2, E7
gpmc_a22 GPMC Address O C2, E8
gpmc_a23 GPMC Address O C1, F6
gpmc_a24 GPMC Address O D1, F7
gpmc_a25 GPMC Address O B4, D2
gpmc_a26 GPMC Address O G8
gpmc_a27 GPMC Address O D8
gpmc_ad0 GPMC Address and Data IO B5
gpmc_ad1 GPMC Address and Data IO A5
gpmc_ad2 GPMC Address and Data IO B6
gpmc_ad3 GPMC Address and Data IO A6
gpmc_ad4 GPMC Address and Data IO B7
gpmc_ad5 GPMC Address and Data IO A7
gpmc_ad6 GPMC Address and Data IO C8
gpmc_ad7 GPMC Address and Data IO B8
gpmc_ad8 GPMC Address and Data IO B10
gpmc_ad9 GPMC Address and Data IO A10
gpmc_ad10 GPMC Address and Data IO F11
gpmc_ad11 GPMC Address and Data IO D11
gpmc_ad12 GPMC Address and Data IO E11
gpmc_ad13 GPMC Address and Data IO C11
gpmc_ad14 GPMC Address and Data IO B11
gpmc_ad15 GPMC Address and Data IO A11
gpmc_advn_ale GPMC Address Valid / Address Latch Enable O A9
gpmc_be0n_cle GPMC Byte Enable 0 / Command Latch Enable O C10
gpmc_be1n GPMC Byte Enable 1 O A3, F10
gpmc_clk GPMC Clock IO A12, B9
gpmc_csn0 GPMC Chip Select O A8
gpmc_csn1 GPMC Chip Select O B9
gpmc_csn2 GPMC Chip Select O F10
gpmc_csn3 GPMC Chip Select O B12
gpmc_csn4 GPMC Chip Select O A2
gpmc_csn5 GPMC Chip Select O B3
gpmc_csn6 GPMC Chip Select O A3
gpmc_dir GPMC Data Direction O A3
gpmc_oen_ren GPMC Output / Read Enable O E10
gpmc_wait0 GPMC Wait 0 I A2, B12
gpmc_wait1 GPMC Wait 1 I A12
gpmc_wen GPMC Write Enable O D10
gpmc_wpn GPMC Write Protect O B3