8.7 LJCB_REFN/P Connections
A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two modes of Common Refclk Rx Architecture are supported:
- External REFCLK Mode: An common external 100MHz clock source is distributed to both the Device and the link partner
- Output REFCLK Mode: A 100MHz HCSL clock source is output by the device and used by the link partner
In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100MHz clock source compliant to the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs.
Alternatively, an LVDS clock source can be used with the following additional requirements:
- External AC coupling capacitors described in Table 8-14 should be populated at the ljcb_clkn / ljcb_clkp inputs.
- All termination requirements (ex. parallel 100ohm termination) from the clock source manufacturer should be followed.
In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External near-side termination to ground described in Table 8-15 is required on both of the ljcb_clkn / ljcb_clkp outputs in this mode.
Table 8-14 LJCB_REFN/P Requirements in External LVDS REFCLK Mode
|ljcb_clkn / ljcb_clkp AC coupling capacitor value
|ljcb_clkn / ljcb_clkp AC coupling capacitor package size
- EIA LxW units, that is, a 0402 is a 40x20 mils surface mount capacitor.
- The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
Table 8-15 LJCB_REFN/P Requirements in Output REFCLK Mode
|ljcb_clkn / ljcb_clkp near-side termination to ground value