Refer to the PDF data sheet for device specific package drawings
Communication between the on-chip processors of the device uses a queued mailbox-interrupt mechanism.
The queued mailbox-interrupt mechanism allows the software to establish a communication channel between two processors through a set of registers and associated interrupt signals by sending and receiving messages (mailboxes).
The device implements the following mailbox types:
Each mailbox module supports the following features:
For more information, see Mailbox chapter in the device TRM.