JAJSW88 データシート

SPRSPA1B March 2025 – November 2025 AM62L

PRODUCTION DATA

1
1 Features
2 Applications
3 Description
1. 3.1 Functional Block Diagram
4 Device Comparison
1. 4.1 Related Products
5 Terminal Configuration and Functions
1. 5.1 Pin Diagrams
2. 5.2 Pin Attributes
  1. 11
  2. 12
3. 5.3 Signal Descriptions
  1. 14
  2. 5.3.1 ADC
    1. 5.3.1.1 MAIN Domain
      1. 17
  3. 5.3.2 CPSW3G
    1. 5.3.2.1 MAIN Domain
      1. 20
      2. 21
      3. 22
      4. 23
  4. 5.3.3 CPTS
    1. 5.3.3.1 MAIN Domain
      1. 26
  5. 5.3.4 DDRSS
    1. 5.3.4.1 MAIN Domain
      1. 29
  6. 5.3.5 DSI
    1. 5.3.5.1 MAIN Domain
      1. 32
  7. 5.3.6 DSS
    1. 5.3.6.1 MAIN Domain
      1. 35
  8. 5.3.7 ECAP
    1. 5.3.7.1 MAIN Domain
      1. 38
      2. 39
      3. 40
  9. 5.3.8 Emulation and Debug
    1. 5.3.8.1 MAIN Domain
      1. 43
    2. 5.3.8.2 WKUP Domain
      1. 45
  10. 5.3.9 EPWM
    1. 5.3.9.1 MAIN Domain
      1. 48
      2. 49
      3. 50
      4. 51
  11. 5.3.10 EQEP
    1. 5.3.10.1 MAIN Domain
      1. 54
      2. 55
      3. 56
  12. 5.3.11 GPIO
    1. 5.3.11.1 MAIN Domain
      1. 59
    2. 5.3.11.2 WKUP Domain
      1. 61
  13. 5.3.12 GPMC
    1. 5.3.12.1 MAIN Domain
      1. 64
  14. 5.3.13 I2C
    1. 5.3.13.1 MAIN Domain
      1. 67
      2. 68
      3. 69
      4. 70
    2. 5.3.13.2 WKUP Domain
      1. 72
  15. 5.3.14 MCAN
    1. 5.3.14.1 MAIN Domain
      1. 75
      2. 76
      3. 77
  16. 5.3.15 MCASP
    1. 5.3.15.1 MAIN Domain
      1. 80
      2. 81
      3. 82
  17. 5.3.16 MCSPI
    1. 5.3.16.1 MAIN Domain
      1. 85
      2. 86
      3. 87
      4. 88
  18. 5.3.17 MDIO
    1. 5.3.17.1 MAIN Domain
      1. 91
  19. 5.3.18 MMC
    1. 5.3.18.1 MAIN Domain
      1. 94
      2. 95
      3. 96
  20. 5.3.19 OSPI
    1. 5.3.19.1 MAIN Domain
      1. 99
  21. 5.3.20 Power Supply
    1. 101
  22. 5.3.21 Reserved
    1. 103
  23. 5.3.22 System and Miscellaneous
    1. 5.3.22.1 Boot Mode Configuration
      1. 5.3.22.1.1 MAIN Domain
        
        107
    2. 5.3.22.2 Clock
      1. 5.3.22.2.1 RTC Domain
        
        110
      2. 5.3.22.2.2 WKUP Domain
        
        112
    3. 5.3.22.3 System
      1. 5.3.22.3.1 MAIN Domain
        
        115
      2. 5.3.22.3.2 RTC Domain
        
        117
      3. 5.3.22.3.3 WKUP Domain
        
        119
  24. 5.3.23 TIMER
    1. 5.3.23.1 MAIN Domain
      1. 122
    2. 5.3.23.2 WKUP Domain
      1. 124
  25. 5.3.24 UART
    1. 5.3.24.1 MAIN Domain
      1. 127
      2. 128
      3. 129
      4. 130
      5. 131
      6. 132
      7. 133
    2. 5.3.24.2 WKUP Domain
      1. 135
  26. 5.3.25 USB
    1. 5.3.25.1 MAIN Domain
      1. 138
      2. 139
4. 5.4 Pin Connectivity Requirements
6 Specifications
7 Detailed Description
8 Applications, Implementation, and Layout
9 Device and Documentation Support
Revision History
10Mechanical, Packaging, and Orderable Information
1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

ANB|373

Thermal pad, mechanical data (Package|Pins)

Orderable Information

sprspa1b_oa

6.11.5.11.2 GPMC and NOR Flash — Asynchronous Mode

Table 6-63 and Table 6-64 present timing requirements and switching characteristics for GPMC and NOR Flash — Asynchronous Mode.

Table 6-63 GPMC and NOR Flash Timing Requirements – Asynchronous Mode see Figure 6-55, Figure 6-56, Figure 6-57, and Figure 6-59

NO.	PARAMETER	DESCRIPTION	MAX	UNIT
FA5⁽¹⁾	t_acc(d)	Data access time	H⁽⁵⁾	ns
FA20⁽²⁾	t_{acc1-pgmode(d)}	Page mode successive data access time	P⁽⁴⁾	ns
FA21⁽³⁾	t_{acc2-pgmode(d)}	Page mode first data access time	H⁽⁵⁾	ns

(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge. FA5 value must be stored inside the AccessTime register bit field.

(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(3) The FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

(4) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾

(5) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽⁶⁾

(6) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

Table 6-64 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode see Figure 6-55, Figure 6-56, Figure 6-57, Figure 6-58, Figure 6-59, and Figure 6-60

NO.	PARAMETER	DESCRIPTION	MIN	MAX	UNIT
FA0	t_w(be[x]nV)	Pulse duration, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid time		N⁽¹²⁾	ns
FA1	t_w(csnV)	Pulse duration, output chip select GPMC_CSn[i]⁽¹³⁾ low		A⁽¹⁾	ns
FA3	t_{d(csnV-advnIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output address valid and address latch enable GPMC_ADVn_ALE invalid	B⁽²⁾ - 2	B⁽²⁾ + 2	ns
FA4	t_{d(csnV-oenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn invalid (Single read)	C⁽³⁾ - 2	C⁽³⁾ + 2	ns
FA9	t_d(aV-csnV)	Delay time, output address GPMC_A[27:1] valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	J⁽⁹⁾ - 2	J⁽⁹⁾ + 2	ns
FA10	t_{d(be[x]nV-csnV)}	Delay time, output lower-byte enable and command latch enable GPMC_BE0n_CLE, output upper-byte enable GPMC_BE1n valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	J⁽⁹⁾ - 2	J⁽⁹⁾ + 2	ns
FA12	t_{d(csnV-advnV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output address valid and address latch enable GPMC_ADVn_ALE valid	K⁽¹⁰⁾ - 2	K⁽¹⁰⁾ + 2	ns
FA13	t_d(csnV-oenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn valid	L⁽¹¹⁾ - 2	L⁽¹¹⁾ + 2	ns
FA16	t_w(aIV)	Pulse duration output address GPMC_A[26:1] invalid between 2 successive read and write accesses	G⁽⁷⁾		ns
FA18	t_{d(csnV-oenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output enable GPMC_OEn_REn invalid (Burst read)	I⁽⁸⁾ - 2	I⁽⁸⁾ + 2	ns
FA20	t_w(aV)	Pulse duration, output address GPMC_A[27:1] valid - 2nd, 3rd, and 4th accesses	D⁽⁴⁾		ns
FA25	t_d(csnV-wenV)	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output write enable GPMC_WEn valid	E⁽⁵⁾ - 2	E⁽⁵⁾ + 2	ns
FA27	t_{d(csnV-wenIV)}	Delay time, output chip select GPMC_CSn[i]⁽¹³⁾ valid to output write enable GPMC_WEn invalid	F⁽⁶⁾ - 2	F⁽⁶⁾ + 2	ns
FA28	t_d(wenV-dV)	Delay time, output write enable GPMC_WEn valid to output data GPMC_AD[15:0] valid		2	ns
FA29	t_d(dV-csnV)	Delay time, output data GPMC_AD[15:0] valid to output chip select GPMC_CSn[i]⁽¹³⁾ valid	J⁽⁹⁾ - 2	J⁽⁹⁾ + 2	ns
FA37	t_d(oenV-aIV)	Delay time, output enable GPMC_OEn_REn valid to output address GPMC_AD[15:0] phase end		2	ns

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
with n being the page burst access number

(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(7) G = Cycle2CycleDelay × GPMC_FCLK⁽¹⁴⁾

(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK⁽¹⁴⁾

(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK⁽¹⁴⁾

(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK⁽¹⁴⁾

(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.

AM62L GPMC and
NOR Flash — Asynchronous Read — Single Word

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock edge. FA5 value must be stored inside AccessTime register bits field.

C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 6-55 GPMC and NOR Flash — Asynchronous Read — Single Word