SPRSP56F January   2021  – October 2023 AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Revision History
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      12
      2.      13
    3. 6.3 Signal Descriptions
      1.      15
      2. 6.3.1  ADC
        1. 6.3.1.1 MAIN Domain
          1.        18
      3. 6.3.2  CPSW3G
        1. 6.3.2.1 MAIN Domain
          1.        21
          2.        22
          3.        23
      4. 6.3.3  CPTS
        1. 6.3.3.1 MAIN Domain
          1.        26
          2.        27
      5. 6.3.4  DDRSS
        1. 6.3.4.1 MAIN Domain
          1.        30
      6. 6.3.5  ECAP
        1. 6.3.5.1 MAIN Domain
          1.        33
          2.        34
          3.        35
      7. 6.3.6  Emulation and Debug
        1. 6.3.6.1 MAIN Domain
          1.        38
        2. 6.3.6.2 MCU Domain
          1.        40
      8. 6.3.7  EPWM
        1. 6.3.7.1 MAIN Domain
          1.        43
          2.        44
          3.        45
          4.        46
          5.        47
          6.        48
          7.        49
          8.        50
          9.        51
          10.        52
      9. 6.3.8  EQEP
        1. 6.3.8.1 MAIN Domain
          1.        55
          2.        56
          3.        57
      10. 6.3.9  FSI
        1. 6.3.9.1 MAIN Domain
          1.        60
          2.        61
          3.        62
          4.        63
          5.        64
          6.        65
          7.        66
          8.        67
      11. 6.3.10 GPIO
        1. 6.3.10.1 MAIN Domain
          1.        70
          2.        71
        2. 6.3.10.2 MCU Domain
          1.        73
      12. 6.3.11 GPMC
        1. 6.3.11.1 MAIN Domain
          1.        76
      13. 6.3.12 I2C
        1. 6.3.12.1 MAIN Domain
          1.        79
          2.        80
          3.        81
          4.        82
        2. 6.3.12.2 MCU Domain
          1.        84
          2.        85
      14. 6.3.13 MCAN
        1. 6.3.13.1 MAIN Domain
          1.        88
          2.        89
      15. 6.3.14 MCSPI
        1. 6.3.14.1 MAIN Domain
          1.        92
          2.        93
          3.        94
          4.        95
          5.        96
        2. 6.3.14.2 MCU Domain
          1.        98
          2.        99
      16. 6.3.15 MDIO
        1. 6.3.15.1 MAIN Domain
          1.        102
      17. 6.3.16 MMC
        1. 6.3.16.1 MAIN Domain
          1.        105
          2.        106
      18. 6.3.17 OSPI
        1. 6.3.17.1 MAIN Domain
          1.        109
      19. 6.3.18 Power Supply
        1.       111
      20. 6.3.19 PRU_ICSSG
        1. 6.3.19.1 MAIN Domain
          1.        114
          2.        115
      21. 6.3.20 Reserved
        1.       117
      22. 6.3.21 SERDES
        1. 6.3.21.1 MAIN Domain
          1.        120
      23. 6.3.22 System and Miscellaneous
        1. 6.3.22.1 Boot Mode Configuration
          1. 6.3.22.1.1 MAIN Domain
            1.         124
        2. 6.3.22.2 Clock
          1. 6.3.22.2.1 MCU Domain
            1.         127
        3. 6.3.22.3 System
          1. 6.3.22.3.1 MAIN Domain
            1.         130
          2. 6.3.22.3.2 MCU Domain
            1.         132
        4. 6.3.22.4 VMON
          1.        134
      24. 6.3.23 TIMER
        1. 6.3.23.1 MAIN Domain
          1.        137
        2. 6.3.23.2 MCU Domain
          1.        139
      25. 6.3.24 UART
        1. 6.3.24.1 MAIN Domain
          1.        142
          2.        143
          3.        144
          4.        145
          5.        146
          6.        147
          7.        148
        2. 6.3.24.2 MCU Domain
          1.        150
          2.        151
      26. 6.3.25 USB
        1. 6.3.25.1 MAIN Domain
          1.        154
    4. 6.4 Pin Connectivity Requirements
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1  I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.7.2  Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 7.7.3  High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 7.7.4  eMMCPHY Electrical Characteristics
      5. 7.7.5  SDIO Electrical Characteristics
      6. 7.7.6  LVCMOS Electrical Characteristics
      7. 7.7.7  ADC12B Electrical Characteristics
      8. 7.7.8  USB2PHY Electrical Characteristics
      9. 7.7.9  SerDes PHY Electrical Characteristics
      10. 7.7.10 DDR Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Requirements
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Power Supply Sequencing
          1. 7.10.2.2.1 Power-Up Sequencing
          2. 7.10.2.2.2 Power-Down Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Safety Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input Clocks / Oscillators
          1. 7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Recommended System Precautions for Clock and Control Signal Transitions
      5. 7.10.5 Peripherals
        1. 7.10.5.1  CPSW3G
          1. 7.10.5.1.1 CPSW3G MDIO Timing
          2. 7.10.5.1.2 CPSW3G RMII Timing
          3. 7.10.5.1.3 CPSW3G RGMII Timing
          4. 7.10.5.1.4 CPSW3G IOSETs
        2. 7.10.5.2  DDRSS
        3. 7.10.5.3  ECAP
        4. 7.10.5.4  EPWM
        5. 7.10.5.5  EQEP
        6. 7.10.5.6  FSI
        7. 7.10.5.7  GPIO
        8. 7.10.5.8  GPMC
          1. 7.10.5.8.1 GPMC and NOR Flash — Synchronous Mode
          2. 7.10.5.8.2 GPMC and NOR Flash — Asynchronous Mode
          3. 7.10.5.8.3 GPMC and NAND Flash — Asynchronous Mode
          4. 7.10.5.8.4 GPMC0 IOSETs
        9. 7.10.5.9  I2C
        10. 7.10.5.10 MCAN
        11. 7.10.5.11 MCSPI
          1. 7.10.5.11.1 MCSPI — Controller Mode
          2. 7.10.5.11.2 MCSPI — Peripheral Mode
        12. 7.10.5.12 MMCSD
          1. 7.10.5.12.1 MMC0 - eMMC Interface
            1. 7.10.5.12.1.1 Legacy SDR Mode
            2. 7.10.5.12.1.2 High Speed SDR Mode
            3. 7.10.5.12.1.3 High Speed DDR Mode
            4. 7.10.5.12.1.4 HS200 Mode
          2. 7.10.5.12.2 MMC1 - SD/SDIO Interface
            1. 7.10.5.12.2.1 Default Speed Mode
            2. 7.10.5.12.2.2 High Speed Mode
            3. 7.10.5.12.2.3 UHS–I SDR12 Mode
            4. 7.10.5.12.2.4 UHS–I SDR25 Mode
            5. 7.10.5.12.2.5 UHS–I SDR50 Mode
            6. 7.10.5.12.2.6 UHS–I DDR50 Mode
            7. 7.10.5.12.2.7 UHS–I SDR104 Mode
        13. 7.10.5.13 CPTS
        14. 7.10.5.14 OSPI
          1. 7.10.5.14.1 OSPI0 PHY Mode
            1. 7.10.5.14.1.1 OSPI0 With PHY Data Training
            2. 7.10.5.14.1.2 OSPI0 Without Data Training
              1. 7.10.5.14.1.2.1 OSPI0 PHY SDR Timing
              2. 7.10.5.14.1.2.2 OSPI0 PHY DDR Timing
          2. 7.10.5.14.2 OSPI0 Tap Mode
            1. 7.10.5.14.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.14.2.2 OSPI0 Tap DDR Timing
        15. 7.10.5.15 PCIe
        16. 7.10.5.16 PRU_ICSSG
          1. 7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)
            1. 7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing
            2. 7.10.5.16.1.2 PRU_ICSSG PRU Parallel Capture Mode Timing
            3. 7.10.5.16.1.3 PRU_ICSSG PRU Shift Mode Timing
            4. 7.10.5.16.1.4 PRU_ICSSG PRU Sigma Delta and Peripheral Interface
              1. 7.10.5.16.1.4.1 PRU_ICSSG PRU Sigma Delta and Peripheral Interface Timing
          2. 7.10.5.16.2 PRU_ICSSG Pulse Width Modulation (PWM)
            1. 7.10.5.16.2.1 PRU_ICSSG PWM Timing
          3. 7.10.5.16.3 PRU_ICSSG Industrial Ethernet Peripheral (IEP)
            1. 7.10.5.16.3.1 PRU_ICSSG IEP Timing
          4. 7.10.5.16.4 PRU_ICSSG Universal Asynchronous Receiver Transmitter (UART)
            1. 7.10.5.16.4.1 PRU_ICSSG UART Timing
          5. 7.10.5.16.5 PRU_ICSSG Enhanced Capture Peripheral (ECAP)
            1. 7.10.5.16.5.1 PRU_ICSSG ECAP Timing
          6. 7.10.5.16.6 PRU_ICSSG RGMII, MII_RT, and Switch
            1. 7.10.5.16.6.1 PRU_ICSSG MDIO Timing
            2. 7.10.5.16.6.2 PRU_ICSSG MII Timing
            3. 7.10.5.16.6.3 PRU_ICSSG RGMII Timing
        17. 7.10.5.17 Timers
        18. 7.10.5.18 UART
        19. 7.10.5.19 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Trace
        2. 7.10.6.2 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A53 Subsystem
      2. 8.2.2 Arm Cortex-R5F Subsystem (R5FSS)
      3. 8.2.3 Arm Cortex-M4F (M4FSS)
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)
    4. 8.4 Other Subsystems
      1. 8.4.1 PDMA Controller
      2. 8.4.2 Peripherals
        1. 8.4.2.1  ADC
        2. 8.4.2.2  DCC
        3. 8.4.2.3  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        4. 8.4.2.4  ECAP
        5. 8.4.2.5  EPWM
        6. 8.4.2.6  ELM
        7. 8.4.2.7  ESM
        8. 8.4.2.8  GPIO
        9. 8.4.2.9  EQEP
        10. 8.4.2.10 General-Purpose Memory Controller (GPMC)
        11. 8.4.2.11 I2C
        12. 8.4.2.12 MCAN
        13. 8.4.2.13 MCRC Controller
        14. 8.4.2.14 MCSPI
        15. 8.4.2.15 MMCSD
        16. 8.4.2.16 OSPI
        17. 8.4.2.17 Peripheral Component Interconnect Express (PCIe)
        18. 8.4.2.18 Serializer/Deserializer (SerDes) PHY
        19. 8.4.2.19 Real Time Interrupt (RTI/WWDT)
        20. 8.4.2.20 Dual Mode Timer (DMTIMER)
        21. 8.4.2.21 UART
        22. 8.4.2.22 Universal Serial Bus Subsystem (USBSS)
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply
        1. 9.1.1.1 Power Supply Designs
        2. 9.1.1.2 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG, EMU, and TRACE
      4. 9.1.4 Unused Pins
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 DDR Board Design and Layout Guidelines
      2. 9.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal SPI devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 Thermal Solution Guidance
    3. 9.3 Clock Routing Guidelines
      1. 9.3.1 Oscillator Routing
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALV|441
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from September 22, 2022 to October 31, 2023 (from Revision E (SEPTEMBER 2022) to Revision F (OCTOBER 2023))

  • (Features): Updated the Security features to clarify what is supportedGo
  • (Features): Corrected broken URL for Functional SafetyGo
  • (Package Information): Updated the table to match the new content standardGo
  • (Functional Block Diagram): Updated URL for Software Build SheetGo
  • (Device Comparison): Updated URL for Software Build SheetGo
  • (Device Comparison): Corrected the name of the JTAG User ID registerGo
  • (Device Comparison): Defined the R5F cores enabled in each device and changed the R5F TCM memory size from "256KB" to "4 x 64KB" in the 2 x Dual Core devices, and "2 x 128KB" in the 2 x Single Core devicesGo
  • (Device Comparison): Added Functional Safety Optional for AM6422Go
  • (Device Comparison): Changed General-Purpose Memory Controller (GPMC) address range from 1GB to 128MBGo
  • (GPMC0 Signal Descriptions): Moved the GPMC0_FCLK_MUX signal from System Signal Descriptions to GPMC0 Signal DescriptionsGo
  • (System Signal Descriptions): Moved the GPMC0_FCLK_MUX signal from System Signal Descriptions to GPMC0 Signal DescriptionsGo
  • (Pin Connectivity Requirements): Updated the second paragraph of the note following the Connectivity Requirements table. The update clarifies the operation of configurable device IOs and includes precautions that must be taken to prevent floating signals from damaging device input buffersGo
  • (Specifications): Remove note that says specifications are preliminary Go
  • (Power-On Hours): Updated the table to match the new content standardGo
  • (Recommended Operating Conditions): Added the Automotive temperature rangeGo
  • (I2C OD FS Electrical Characteristics): Changed the IOL minimum value from 20 to 10 for both 1.8 V and 3.3 V modesGo
  • (DDR Electrical Characteristics): Added references to the respective JEDEC standardsGo
  • (System Timing): Removed the Timing Conditions table from this section and added separate Timing Conditions tables to each of the Reset Timing, Safety Signal Timing, and Clock Timing sectionsGo
  • (Reset Timing): Added Timing Conditions table to define conditions specific to reset inputs and outputsGo
  • (MCU_RESETSTATz, and RESETSTATz Switching Characteristics): Changed the minimum value of parameter RST8 from "4040*S" to "966*S" and the minimum value of parameter RST9 from "301200" to "4040*S".Go
  • (MCU_RESETSTATz, and RESETSTATz Switching Characteristics): Changed the minimum value of parameter RST13 from "0" to "960".Go
  • (RESETSTATz Switching Characteristics): Changed the minimum value of parameter RST16 from "T" to "900*T", the minimum value of parameter RST17 from "W" to "4040*S", and replaced the contents of table note 2.Go
  • (PORz_OUT Switching Characteristics): Changed the minimum value of parameter RST26 from "0" to "1840".Go
  • (Safety Signal Timing): Added Timing Conditions table to define conditions specific to MCU_SAFETY_ERRORn output...Go
  • (MCU_ERRORn Switching Characteristics): Changed "RST22" to "SFTY3" in table note 5.Go
  • (Clock Timing): Added Timing Conditions table to define conditions specific to clock inputs and outputsGo
  • (Clock Timing Requirements): Updated the Timing Requirements figure with a single generic waveform and updated the parameter numbers in the Timing Requirements table to reference the generic clock waveformGo
  • (Clock Switching Characteristics): Updated the Switching Characteristics figure with a single generic waveform and updated the parameter numbers in the Switching Characteristics table to reference the generic clock waveformGo
  • (MCU_OSC0 Crystal Implementation): Changing the crystal oscillator circuit diagram back to the original version used in previous revisions of this documentGo
  • Removing change item for change that was already implemented in a previous release of both AM64x and AM243x and prevent the change from showing up again in the current Revision History.Go
  • (CPSW3G MDIO Timing): Included PCB Connectivity Requirements in the Timing Conditions table, changed the minimum setup time value (parameter MDIO1) from "90" to "45", and changed the minimum and maximum output delay time values (parameter MDIO7) from "-150" and "150" to "-10" and "10" respectivelyGo
  • (GPMC0 IOSETs): Removed GPMC0_CLKLB since there is no pin with this name Go
  • (MCSPI Switching Characteristics - Controller Mode): Replaced previous table notes 2 and 3 with new table notes 2, 3, 4, and 5Go
  • (MMC0 Timing Requirements – Legacy SDR Mode): Changed the minimum values for LSDR1 and LSDR3 from 9.69 to 1.56, and the minimum values for LSDR2 and LSDR4 from 27.97 to 5.44Go
  • (MMC0 Switching Characteristics – Legacy SDR Mode): Changed the minimum values for LSDR8 and LSDR9 from -16.1 to -2.3, and the maximum values for HSSDR8 and HSSDR9 from 16.1 to 2.9Go
  • (MMC0 Timing Requirements – High Speed SDR Mode): Changed the minimum values for HSSDR1 and HSSDR3 from 2.99 to 2.55Go
  • (MMC0 Switching Characteristics – High Speed SDR Mode): Changed the minimum values for HSSDR8 and HSSDR9 from -6.35 to -2.3, and the maximum values for HSSDR8 and HSSDR9 from 6.35 to 2.9Go
  • (MMC0 Timing Requirements – High Speed DDR Mode): Changed the minimum values for HSDDR1 from 3.88 to 1.62, and the minimum values for HSDDR2 from 2.67 to 2.52Go
  • (MMC0 Switching Characteristics – High Speed DDR Mode): Changed the maximum value for HSDDR8 from 16.19 to 7.65Go
  • (MMC1 DLL Delay Mapping for All Timing Modes): Changed the value of OTAPDLYENA from 0x0 to 0x1 for Default Speed and High Speed modes. Also changed UHS-I DR50 to UHS-I DDR50 to correct a typographical error in the mode nameGo
  • (Timing Requirements for MMC1 – Default Speed Mode): Changed the minimum values for DS1 and DS3 from 2.55 to 2.15, and the minimum values for DS2 and DS2 from 19.67 to 1.67Go
  • (Switching Characteristics for MMC1 – Default Speed Mode): Changed the minimum values for DS8 and DS9 from -14.1 to -1.8, and the maximum values for DS8 and DS9 from 14.1 to 1.8Go
  • (Timing Requirements for MMC1 – High Speed Mode): Changed the minimum values for HS1 and HS3 from 2.55 to 2.15, and the minimum values for HS2 and HS2 from 2.67 to 1.67Go
  • (Switching Characteristics for MMC1 – High Speed Mode): Changed the minimum values for HS8 and HS9 from -7.35 to -1.8, and the maximum values for HS8 and HS9 from 3.35 to 1.8Go
  • (Timing Requirements for MMC1 – UHS-I SDR12 Mode): Changed the minimum values for SDR121 and SDR123 from 21.65 to 2.35Go
  • (Switching Characteristics for MMC1 – UHS-I SDR12 Mode): Changed the minimum values for SDR128 and SDR129 from -13.6 to 1.2, and the maximum values for SDR128 and SDR129 from 13.6 to 8Go
  • (Timing Requirements for MMC1 – UHS-I SDR25 Mode): Changed the minimum values for SDR251 and SDR253 from 2.15 to 1.95Go
  • (Switching Characteristics for MMC1 – UHS-I SDR25 Mode): Changed the minimum values for SDR258 and SDR259 from -7.1 to 2.4, and the maximum values for SDR258 and SDR259 from 3.1 to 8Go
  • (Timing Requirements for MMC1 – UHS-I DDR50 Mode): Removed Timing Requirements since the UHS-I DDR50 mode requires a tuning algorithm to be used for optimal input timingGo
  • (Switching Characteristics for MMC1 – UHS-I DDR50 Mode): Changed the maximum value for DDR508 from 13.1 to 6.35Go
  • (Switching Characteristics for MMC1 – UHS-I SDR104 Mode): Changed the minimum values for SDR1046 and SDR1047 from 2.08 to 2.12, the minimum values for SDR1048 and SDR1049 from 1.12 to 1.08, and maximum values for SDR1048 and SDR1049 from 3.16 to 3.2Go
  • (OSPI0 With PHY Data Training): Added a missing comma between the second and third XREF in the third paragraphGo
  • (OSPI Switching Characteristics – PHY Data Training): Added maximum values to the OSPI0_CLK Cycle Time parameter (O1) to define a minimum operating frequency of 133MHz. Also updated Note 1 and Note 4, where "in ns" was added to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it matches the clock name used in the TRMGo
  • (OSPI0 Switching Characteristics – PHY SDR Mode): Updated Note 1 and Note 4, where "in ns" was added to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it matches the clock name used in the TRMGo
  • (OSPI0 Switching Characteristics – PHY DDR Mode): Updated Note 1 and Note 4, where "in ns" was added to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it matches the clock name used in the TRMGo
  • (OSPI0 Timing Requirements – Tap SDR Mode): Updated the constant values associated with the minimum setup and minimum hold formulas in parameters O19 and O20. Note 2 was also updated to change "refclk" to "reference clock" so it matches the clock name used in the TRMGo
  • (OSPI0 Switching Characteristics – Tap SDR Mode): Updated Note 1 and Note 4, where "in ns" was added to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 4 so it matches the clock name used in the TRMGo
  • (OSPI0 Timing Requirements – Tap DDR Mode): Updated the constant values associated with the minimum setup and minimum hold formulas in parameters O13 and O14. Note 2 was also updated to change "refclk" to "reference clock" so it matches the clock name used in the TRMGo
  • (OSPI0 Switching Characteristics – Tap DDR Mode): Changed the "OSPI_RD_DATA_CAPTURE_REG" bit field from "DELAY_FLD" to "DDR_READ_DELAY_FLD" in the note associated with parameter O6Go
  • (OSPI0 Switching Characteristics – Tap DDR Mode): Updated the minimum data output delay and maximum data output delay formulas in parameter O6. Also updated Note 1 and Note 5, where "in ns" was added to the OSPI_CLK cycle time reference in Note 1 and "refclk" was changed to "reference clock" in Note 5 so it matches the clock name used in the TRMGo
  • (PCIe): Updated the "For more details about features and ..." paragraph.Go
  • (PRUSS PRU Switching Characteristics – Direct Output Mode): Changed the maximum skew value for the GPO to GPO parameter (PRDO1) from 3ns to 2nsGo
  • (PRU_ICSSG UART Timing Conditions): applied small changes to tablenote 1Go
  • (PRU_ICSSG UART Switching Characteristics): Added the TRM UART baud rate settings reference to Note 1Go
  • (USB): Updated the "For more details about features and ..." paragraph.Go
  • (Power Supply Designs): Updated recommended PMIC from LP8733xx to TPS65220 or TPS65219Go
  • (USB VBUS Design Guidelines): Changed the 3.5 kΩ resistor value to 3.48kΩ since 3.5kΩ is not a standard value for 1% resistorsGo
  • (Clock Routing Guidelines): Added new sectionGo
  • (Device Naming Convention): Added the Automotive temperature rangeGo