SBAS654G June   2014  – January 2020 AMC1305L25 , AMC1305M05 , AMC1305M25

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: AMC1305M05
    10. 7.10 Electrical Characteristics: AMC1305x25
    11. 7.11 Switching Characteristics
    12. 7.12 Insulation Characteristics Curves
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Modulator
      3. 8.3.3 Digital Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Output
      2. 8.4.2 Output Behavior in Case of Full-Scale Input
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Filter Usage
    2. 9.2 Typical Applications
      1. 9.2.1 Frequency Inverter Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Isolated Voltage Sensing
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.9 Electrical Characteristics: AMC1305M05

All minimum and maximum specifications at TA = –40°C to +125°C, AVDD = 4.5 V to 5.5 V, DVDD = 3.0 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted. Typical values are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5.0 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
VClipping Maximum differential voltage input range
(AINP-AINN)		 ±62.5 mV
FSR Specified linear full-scale range
(AINP-AINN)		 –50 50 mV
VCM Operating common-mode input range –0.032 AVDD – 2 V
CID Differential input capacitance 2 pF
IIB Input current Inputs shorted to AGND –97 –72 -57 μA
RID Differential input resistance 5 kΩ
IOS Input offset current ±5 nA
CMTI Common-mode transient immunity 15 kV/μs
CMRR Common-mode rejection ratio fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max 		–104 dB
fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max 		–75
BW Input bandwidth 800 kHz
DC ACCURACY
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
INL Integral nonlinearity(3) Resolution: 16 bits –4 ±1.5 4 LSB
EO Offset error Initial, at 25°C –50 ±2.5 50 µV
TCEO Offset error thermal drift(1) –1.3 1.3 μV/°C
EG Gain error Initial, at 25°C –0.3% –0.02% 0.3%
TCEG Gain error thermal drift(2) –40 ±20 40 ppm/°C
PSRR Power-supply rejection ratio VAVDD from 4.5 to 5.5V, at dc 105 dB
AC ACCURACY
SNR Signal-to-noise ratio fIN = 1 kHz 76 81 dB
SINAD Signal-to-noise + distortion fIN = 1 kHz 76 81 dB
THD Total harmonic distortion fIN = 1 kHz –90 –83 dB
SFDR Spurious-free dynamic range fIN = 1 kHz 83 92 dB
DIGITAL INPUTS/OUTPUTS
External Clock
fCLKIN Input clock frequency 5 20 20.1 MHz
DutyCLKIN Duty cycle 5 MHz ≤ fCLKIN ≤ 20.1 MHz 40% 50% 60%
CMOS Logic Family, CMOS with Schmitt-Trigger
IIN Input current DGND ≤ VIN ≤ DVDD –1 1 μA
CIN Input capacitance 5 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × DVDD V
CLOAD Output load capacitance fCLKIN = 20 MHz 30 pF
VOH High-level output voltage IOH = –20 µA DVDD – 0.1 V
IOH = –4 mA DVDD – 0.4
VOL Low-level output voltage IOL = 20 µA 0.1 V
IOL = 4 mA 0.4
POWER SUPPLY
AVDD High-side supply voltage 4.5 5.0 5.5 V
IAVDD High-side supply current 6.5 8.2 mA
PAVDD High-side power dissipation 32.5 45.1 mW
DVDD Controller-side supply voltage 3.0 3.3 5.5 V
IDVDD Controller-side supply current 3.0 V ≤ DVDD ≤ 3.6 V 2.7 4.0 mA
4.5 V ≤ DVDD ≤ 5.5 V 3.2 5.5
PDVDD Controller-side power dissipation 3.0 V ≤ DVDD ≤ 3.6 V 8.9 14.4 mW
4.5 V ≤ DVDD ≤ 5.5 V 16.0 30.3
(1) Offset error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_eodrift_bas654.gif
(2) Gain error drift is calculated using the box method as described by the following equation: AMC1305L25 AMC1305M05 AMC1305M25 ec_egdrift_bas654.gif
(3) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.