SBASA35A June   2020  – October 2020 AMC3330-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagram
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Isolation Channel Signal Transmission
      3. 7.3.3 Analog Output
      4. 7.3.4 Isolated DC/DC Converter
      5. 7.3.5 Diagnostic Output and Fail-Safe Behavior
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filter Design
        2. 8.2.2.2 Differential to Single-Ended Output Conversion
      3. 8.2.3 Application Curve
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C, VDD = 3.0 V to 5.5 V, INP = –1 V to +1 V, and INN = HGND = 0 V; typical specifications are at TA = 25°C, and VDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
RIN Single-ended input resistance INN = HGND 0.1 0.8 GΩ
RIND Differential input resistance 0.1 1.2
IIB Input bias current INP = INN = HGND, IIB = (IIBP + IIBN) / 2 –10 2.5 10 nA
TCIIB Input bias current drift –14 pA/°C
IIO Input offset current IIO = IINP – IINN; INP = INN = HGND –10 -0.8 10 nA
CIN Single-ended input capacitance INN = HGND, fIN = 310 kHz 2 pF
CIND Differential input capacitance fIN = 310 kHz 2
ANALOG OUTPUT
Nominal gain 2
VCMout Common-mode output voltage 1.39 1.44 1.49 V
VCLIPout Clipping differential output voltage VOUT = (VOUTP – VOUTN);
|VIN| = |VINP – VINN| > VClipping 		±2.49 V
VFailsafe Fail-safe differential output voltage V+ = (VOUTP – VOUTN); VDCDCout ≤ VDCDCUV or VHLDOout ≤ VHLDOUV –2.57 –2.5 V
BWOUT Output bandwidth 300 375 kHz
ROUT Output resistance On OUTP or OUTN 0.2 Ω
Output short-circuit current On OUTP or OUTN, sourcing or sinking, INP = INN = HGND, outputs shorted to either GND or VDD 14 mA
CMTI Common-mode transient immunity |HGND – GND| = 2 kV 85 135 kV/µs
ACCURACY
EG Gain error TA = 25°C –0.2% –0.08% 0.2%
TCEG Gain error drift(1) –45 ±7 45 ppm/°C
VOS Input offset voltage(1) TA = 25°C, INP = INN = HGND –0.3 ±0.05 0.3 mV
TCVOS Input offset drift(1) –4 ±1 4 µV/°C
Nonlinearity –0.02% 0.01% 0.02%
Nonlinearity drift 0.4 ppm/°C
SNR Signal-to-noise ratio VIN = 2 VPP, fIN = 1 kHz,
BW = 10 kHz, 10 kHz filter		 81 85 dB
VIN = 2 VPP, fIN = 10 kHz,
BW = 100 kHz, 1 MHz filter		 72
THD Total harmonic distortion VIN = 2 Vpp, fIN = 10 kHz,
BW = 100 kHz		 –84 dB
Output noise INP = INN = HGND, fIN = 0 Hz,
BW = 100 kHz		 250 µVRMS
CMRR Common-mode rejection ratio fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max –100 dB
fIN = 10 kHz, VCM min ≤ VCM ≤ VCM max –86
PSRR Power-supply rejection ratio VDD from 3.0 V to 5.5 V, at dc, input referred –98 dB
INP = INN = HGND, VDD from 3.0 V to 5.5 V, 10 kHz / 100 mV ripple, input referred –86
POWER SUPPLY
IDD Low-side supply current No external load on HLDO 28.5 41 mA
1 mA  external load on HLDO 30.5 43 mA
VDCDC_OUT DC/DC output voltage DCDC_OUT to HGND 3.1 3.5 4.65 V
VDCDCUV DC/DC output undervoltage detection threshold voltage DCDC output falling 2.1 2.25 V
VHLDO_OUT High-side LDO output voltage HLDO to HGND, up to 1 mA external load 3 3.2 3.4 V
VHLDOUV High-side LDO output undervoltage detection threshold voltage HLDO output falling 2.4 2.6 V
IH High-side supply current for auxiliary circuitry Load connected from HLDO_OUT to HGND; non-switching 1 mA
tAS Analog settling time VDD step to 3.0 V, to OUTP and OUTN valid, 0.1% settling 0.6 1.1 ms
(1) The typical value includes one standard deviation ("sigma") at nominal operating conditons.