SWRS188C May   2017  – April 2020 AWR1243

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Supply Specifications
    6. 5.6 Power Consumption Summary
    7. 5.7 RF Specification
    8. 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Power Supply Sequencing and Reset Timing
      2. 5.9.2 Synchronized Frame Triggering
      3. 5.9.3 Input Clocks and Oscillators
        1. 5.9.3.1 Clock Specifications
      4. 5.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.9.4.1 Peripheral Description
          1. Table 5-8  SPI Timing Conditions
          2. Table 5-9  SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. Table 5-10 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 5.9.4.2 Typical Interface Protocol Diagram (Slave Mode)
      5. 5.9.5 LVDS Interface Configuration
        1. 5.9.5.1 LVDS Interface Timings
      6. 5.9.6 General-Purpose Input/Output
        1. Table 5-12 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 5.9.7 Camera Serial Interface (CSI)
        1. Table 5-13 CSI Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Host Interface
    4. 6.4 Other Subsystems
      1. 6.4.1 A2D Data Format Over CSI2 Interface
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Short-, Medium-, and Long-Range Radar
    3. 7.3 Imaging Radar using Cascade Configuration
    4. 7.4 Reference Schematic
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-13 CSI Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
HPTX
HSTXDBR Data bit rate (1/2/4 data lane PHY) 150 600 Mbps
fCLK DDR clock frequency (1/2/4 data lane PHY) 75 300 MHz
ΔVCMTX(LF) Common-level variation –50 50 mV
tR and tF 20% to 80% rise time and fall time 0.3 UI
LPTX DRIVER
tEOT Time from start of THS-TRAIL period to start of LP-11 state 105 + 12*UI ns
DATA-CLOCK Timing Specification
UINOM Nominal Unit Interval 1.67 13.33 ns
UIINST,MIN Minimum instantaneous Unit Interval 1.131 ns
TSKEW[TX] Data to clock skew measured at transmitter –0.15 0.15 UIINST,MIN
CSI2 TIMING SPECIFICATION
TCLK-PRE Time that the HS clock shall be driven by the transmitter before any associated data lane beginning the transition from LP to HS mode. 8 ns
TCLK-PREPARE Time that the transmitter drives the clock lane LP-00 line state immediately before the HS-0 line state starting the HS transmission. 38 95 ns
TCLK-PREPARE + TCLK-ZERO TCLK-PREPARE + time that the transmitter drives the HS-0 state before starting the clock. 300 ns
TEOT Transmitted time interval from the start of THS-TRAIL or TCLKTRAIL, to the start of the LP-11 state following a HS burst. 105 ns + 12*UI ns
THS-PREPARE Time that the transmitter drives the data lane LP-00 line state immediately before the HS-0 line state starting the HS transmission 40 + 4*UI 85 + 6*UI ns
THS-PREPARE + THS-ZERO THS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. 145 ns + 10*UI ns
THS-EXIT Time that the transmitter drives LP-11 following a HS burst. 100 ns
THS-TRAIL Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst max(8*UI, 60 ns + 4*UI) ns
TLPX TXXXransmitted length of any low-power state period 50 ns
AWR1243 clock_and_data_timing.gifFigure 5-9 Clock and Data Timing in HS Transmission
AWR1243 30188403.gifFigure 5-10 High-Speed Data Transmission Burst
AWR1243 clock_lane_switching.gif
1. The HS to LP transition of the CLK does not actually take place since the CLK is always ON in HS mode.
Figure 5-11 Switching the Clock Lane Between Clock Transmission and Low-Power Mode