SWRS188C May   2017  – April 2020 AWR1243

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Supply Specifications
    6. 5.6 Power Consumption Summary
    7. 5.7 RF Specification
    8. 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1 Power Supply Sequencing and Reset Timing
      2. 5.9.2 Synchronized Frame Triggering
      3. 5.9.3 Input Clocks and Oscillators
        1. 5.9.3.1 Clock Specifications
      4. 5.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.9.4.1 Peripheral Description
          1. Table 5-8  SPI Timing Conditions
          2. Table 5-9  SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. Table 5-10 SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 5.9.4.2 Typical Interface Protocol Diagram (Slave Mode)
      5. 5.9.5 LVDS Interface Configuration
        1. 5.9.5.1 LVDS Interface Timings
      6. 5.9.6 General-Purpose Input/Output
        1. Table 5-12 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 5.9.7 Camera Serial Interface (CSI)
        1. Table 5-13 CSI Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Host Interface
    4. 6.4 Other Subsystems
      1. 6.4.1 A2D Data Format Over CSI2 Interface
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Short-, Medium-, and Long-Range Radar
    3. 7.3 Imaging Radar using Cascade Configuration
    4. 7.4 Reference Schematic
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]

 
THERMAL METRICS(1) °C/W(2)(3)
RΘJC Junction-to-case 5
RΘJB Junction-to-board 5.9
RΘJA Junction-to-free air 21.6
RΘJMA Junction-to-moving air 15.3(4)
PsiJT Junction-to-package top 0.69
PsiJB Junction-to-board 5.8
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) °C/W = degrees Celsius per watt.
(3) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:
  • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
  • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
A junction temperature of 125ºC is assumed.
(4) Air flow = 1 m/s