18.104.22.168 Typical Interface Protocol Diagram (Slave Mode)
- Host should ensure that there is a delay of at least two SPI clocks between CS going low and start of SPI clock.
- Host should ensure that CS is toggled for every 16 bits of transfer through SPI.
Figure 5-6 shows the SPI communication timing of the typical interface protocol.
Figure 5-6 SPI Communication