SWRS203C May   2017  – December 2021 AWR1642

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Functional Block Diagram
  5. Revision History
  6. Device Comparison
    1. 6.1 Related Products
  7. Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions - Digital
      2. 7.2.2 Signal Descriptions - Analog
    3. 7.3 Pin Attributes
  8. Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Power Supply Sequencing and Reset Timing
      2. 8.10.2  Input Clocks and Oscillators
        1. 8.10.2.1 Clock Specifications
      3. 8.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.3.1 Peripheral Description
        2. 8.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.3.2.1 SPI Timing Conditions
          2. 8.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
          3. 8.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) (1) (1) (1)
        3. 8.10.3.3 SPI Peripheral Mode I/O Timings
          1. 8.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 8.10.4  LVDS Interface Configuration
        1. 8.10.4.1 LVDS Interface Timings
      5. 8.10.5  General-Purpose Input/Output
        1. 8.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 8.10.6  Controller Area Network Interface (DCAN)
        1. 8.10.6.1 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 8.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 8.10.8  Serial Communication Interface (SCI)
        1. 8.10.8.1 SCI Timing Requirements
      9. 8.10.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.10.9.1 I2C Timing Requirements (1)
      10. 8.10.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.10.10.1 QSPI Timing Conditions
        2. 8.10.10.2 Timing Requirements for QSPI Input (Read) Timings (1) (1)
        3. 8.10.10.3 QSPI Switching Characteristics
      11. 8.10.11 ETM Trace Interface
        1. 8.10.11.1 ETMTRACE Timing Conditions
        2. 8.10.11.2 ETM TRACE Switching Characteristics
      12. 8.10.12 Data Modification Module (DMM)
        1. 8.10.12.1 DMM Timing Requirements
      13. 8.10.13 JTAG Interface
        1. 8.10.13.1 JTAG Timing Conditions
        2. 8.10.13.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.13.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Automotive Interface
      4. 9.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 9.3.5 DSP Subsystem Memory Map
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Short-Range Radar
    3. 11.3 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from May 1, 2020 to December 30, 2021 (from Revision B (May 2020) to Revision C (December 2021 ))

  • Section 1 (Features): Updated/Changed the RX noise figure value from "14" to "12" dbGo
  • (Features): Updated/Changed the Phase noise at 1-MHz value from "–92 " to "–93" dBc/HzGo
  • Global: Updated to reflect Functional Safety-ComplianceGo
  • Global: Replaced "A2D" with "ADC"; Changed Masters Subsystem and Masters R4F to Main Subsystem and Main R4F; Shift to more inclusive langauge made in terms of Master/Slave terminologyGo
  • (Features) : Updated Functional-Safety Compliance Certification Collateral; Mentioned the specific operating temperature range for the mmWave Sensor; Additional information on Device Security updated. Go
  • (Device Information) : Additional Secure production parts added for the mmWave SensorGo
  • Updated/Changed Functional Block Diagram for inclusive terminologyGo
  • (Device Comparison): Removed a row on Functional-Safety compliance and instead added a table-note for this and LVDS Interface; Additional information on Device security addedGo
  • (Signal Descriptions) :Updated/Changed CLKP and CLKM descriptionsGo
  • (Pin Attributes): Updated/Changed table to remove unsupported mux modes and deleted unsupported CAN signal names.Go
  • (Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and a table-note for the signal level applied on TX.Go
  • (Clock Specifications): Updated/Changed Table 8-5 to reflect correct device operating temperature range.Go
  • (Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppmGo
  • Added a footnote for L3-Shared memory in DSP C674x Memory Map Go
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateralGo
  • (Reference Schematics) : Added weblinks to device EVM documentation collateral Go
  • (Device Nomenclature):Updated/changed Device Nomenclature Go