SWRS203B May 2017 – April 2020 AWR1642
Refer to the PDF data sheet for device specific package drawings
The AWR1642 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF synthesizer is then processed by an X4 multiplier to create the required frequency in the 76 to 81 GHz spectrum. The RF synthesizer output is modulated by the timing engine block to create the required waveforms for effective sensor operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring the quality of the generated clock.
Figure 6-2 describes the clock subsystem.