SWRS203B May   2017  – April 2020 AWR1642

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1 Related Products
  4. Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-3 PAD IO Register Bit Descriptions
    3. 4.3 Signal Descriptions
      1. Table 4-4 Signal Descriptions - Digital
      2. Table 4-5 Signal Descriptions - Analog
  5. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Supply Specifications
    6. 5.6  Power Consumption Summary
    7. 5.7  RF Specification
    8. 5.8  CPU Specifications
    9. 5.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1  Power Supply Sequencing and Reset Timing
      2. 5.10.2  Input Clocks and Oscillators
        1. 5.10.2.1 Clock Specifications
      3. 5.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.10.3.1 Peripheral Description
        2. 5.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-7 SPI Timing Conditions
          2. Table 5-8 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-9 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.10.3.3 SPI Slave Mode I/O Timings
          1. Table 5-10 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 5.10.4  LVDS Interface Configuration
        1. 5.10.4.1 LVDS Interface Timings
      5. 5.10.5  General-Purpose Input/Output
        1. Table 5-12 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 5.10.6  Controller Area Network Interface (DCAN)
        1. Table 5-13 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 5.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. Table 5-14 Dynamic Characteristics for the CANx TX and RX Pins
      8. 5.10.8  Serial Communication Interface (SCI)
        1. Table 5-15 SCI Timing Requirements
      9. 5.10.9  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-16 I2C Timing Requirements
      10. 5.10.10 Quad Serial Peripheral Interface (QSPI)
        1. Table 5-17 QSPI Timing Conditions
        2. Table 5-18 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-19 QSPI Switching Characteristics
      11. 5.10.11 ETM Trace Interface
        1. Table 5-20 ETMTRACE Timing Conditions
        2. Table 5-21 ETM TRACE Switching Characteristics
      12. 5.10.12 Data Modification Module (DMM)
        1. Table 5-22 DMM Timing Requirements
      13. 5.10.13 JTAG Interface
        1. Table 5-23 JTAG Timing Conditions
        2. Table 5-24 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-25 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Processor Subsystem
      3. 6.3.3 Automotive Interface
      4. 6.3.4 Master Subsystem Cortex-R4F Memory Map
      5. 6.3.5 DSP Subsystem Memory Map
    4. 6.4 Other Subsystems
      1. 6.4.1 ADC Channels (Service) for User Application
        1. Table 6-3 GP-ADC Parameter
  7. Monitoring and Diagnostics
    1. 7.1 Monitoring and Diagnostic Mechanisms
      1. 7.1.1 Error Signaling Module
  8. Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Short-Range Radar
    3. 8.3 Reference Schematic
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Stackup Details
  9. Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from April 30, 2018 to April 30, 2020 (from A Revision (April 2018) to B Revision)

  • Global: Added/Updated Functional Safety-Compliant targeted informationGo
  • Global: Deleted the Export Control Notice section (was Section 9.7).Go
  • Section 1.1 (Features): Updated/Changed TX Power from "12.5 dBm" to "12 dBm"Go
  • Section 1.1: Updated/Changed subbullet to "CAN and CAN-FD"Go
  • Section 1.2 (Applications): Updated/Changed ApplicationsGo
  • Figure 1-2 (Functional Block Diagram): Updated/Changed figure - deleted Debug from UARTs block.Go
  • Section 3 (Device Comparison): Deleted the AWR1243P device from the table and updated the associated footnote.Go
  • Section 3: Updated/Changed the Hardware accelerator to "Yes" for AWR1843.Go
  • Section 3: Changed AWR1243 and AWR1443 Product status from AI to PDGo
  • Section 3.1 (Related Products): Updated/Changed page links for both "mmWave sensors" and "Automotive mmWave sensors".Go
  • Table 4-1 (Pin Attributes (ABL0161 Package): Corrected BALL NUMBER C13 MODE 0 "SPIA_cs_n" (duplicate) to "GPIO_30" SIGNAL NAME.Go
  • Table 4-1: Corrected BALL NUMBER F14 MODE 1 "SPIB-clk1" to "SPIB-clk" SIGNAL NAME.Go
  • Section 4.3 (Signal Descriptions): Added NOTE about IO pins.Go
  • Section 4.3: Added NOTE on the GPIO state during power supply rampGo
  • Table 4-4: Added missing DESCRIPTIONS to the EPWMxSYNC SIGNAL NAME rowsGo
  • Table 4-5 (Signal Descriptions - Analog): Updated/Changed "1.8" to "1.4" V in OSC_CLKOUT DESCRIPTIONGo
  • Section 5.1 (Absolute Maximum Ratings): Added parametric MAX values for both externally applied power on RF inputs and outputsGo
  • Section 5.2 (ESD Ratings): Updated/Changed HBM value from "±1000" to "±2000" V.Go
  • Section 5.2: Updated/Changed CDM value from "±250" to "±500". V.Go
  • Section 5.3 (Power-On Hours (POH)): Added applicable "default firmware gain tables" footnote.Go
  • Section 5.4 (Recommended Operating Conditions): Updated/Changed MIN value for VIOIN (IO supply (3.3 V) from "3.15" to "3.135" V.Go
  • Section 5.4: Updated/Changed MAX value for VIOIN (IO supply (3.3 V) from "3.45" to "3.465" V.Go
  • Table 5-2 (Ripple Specifications): Updated/Changed the lead-in paragraph.Go
  • Table 5-2: Updated/Changed 137.5 FREQUENCY, 1.0 V RF RAIL value from "744" to "7" µVRMS.Go
  • Table 5-2: Updated/Changed 275 FREQUENCY, 1.0 V RF RAIL value from "4" to "5" µVRMS.Go
  • Table 5-3 (Maximum Current Ratings at Power Terminals): Moved VIOIN "50" mA MAX value to TYP column.Go
  • Table 5-3: Added "The exact VIOIN current ..." footnote.Go
  • Table 5-3: Added "specified current values ..." footnote.Go
  • Table 5-3: Updated footnote to Maximum Current Ratings at Power TerminalsGo
  • Section 5.7 (RF Specification): Updated/Changed the operating conditions statement for table parameters.Go
  • Section 5.7: Updated/Changed the MMR TYP value of "21" to "30" dB. parameters.Go
  • Section 5.7: Updated/Changed the In-band IIP2 TYP value from "20" to "16" dBm.Go
  • Section 5.7: Updated/Changed the Out-of-band IIP2 TYP value from "35" to "24" dBm.Go
  • Section 5.7: Updated/Changed the Transmitter, Output power TYP value from "12.5" to "12" dBm.Go
  • Section 5.9 (Thermal Resistance Characteristics for FCBGA Package [ABL0161]): Updated/Changed all thermal resistance values for ABL package and changed associated Air flow footnote.Go
  • Section 5.10.1 (Power Supply Sequencing and Reset Timing): Updated/Changed the section.Go
  • Figure 5-2 (Device Wake-up Sequence): Updated/Changed figure.Go
  • Table 5-5: Updated/Changed fP Parallel resonance crystal frequency from " 40, 50" to "40" MHzGo
  • Section 5.10.4 (LVDS Interface Configuration): Added "The LVDS interface is used ..." sentence to the lead-in paragraph.Go
  • Figure 5-11 (LVDS Interface Lane Configuration And Relative Timings): Updated image.Go
  • Table 5-11 (LVDS Electrical Characteristics): Updated/Changed characteristics table Go
  • Figure 5-12 (Timing Parameters): Updated/Changed figure.Go
  • Figure 6-3 (Transmit Subsystem (Per Channel)): Updated/Changed figure.Go
  • Figure 6-4 (Receive Subsystem (Per Channel)): Updated/Changed figure.Go
  • Section 6.3.3 (Automotive Interface): Updated/Changed bullet to "CAN and CAN-FD".Go
  • Table 6-1 (Master Subsystem, Cortex-R4F Memory Map): Updated/Changed the TCM RAM-A SIZE and DESCRIPTIONGo
  • Figure 6-6 (ADC Path): Updated/Changed the accuracy of these measurements from "±10" to "±7" ºC.Go
  • Section 7.1 (Monitoring and Diagnostic Mechanisms): Updated/Changed the lead-in sentence.Go
  • Table 7-1 (Monitoring and Diagnostic Mechanisms for AWR1642): Updated/Changed the "RX loopback test" feature DESCRIPTION.Go
  • Section 8.3 (Reference Schematic): Updated/Changed the VBGAP decoupling capacitor value from "0.22 uF" to "47 nF".Go
  • Section 9.4 (Support Resources): Updated/Changed the section title and revamped the sectionGo