SWRS222B December   2018  – April 2020 AWR1843

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1 Related Products
  4. Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-3 PAD IO Register Bit Descriptions
    3. 4.3 Signal Descriptions
      1. Table 4-4 Signal Descriptions - Digital
      2. Table 4-5 Signal Descriptions - Analog
  5. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Supply Specifications
    6. 5.6  Power Consumption Summary
    7. 5.7  RF Specification
    8. 5.8  CPU Specifications
    9. 5.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1  Power Supply Sequencing and Reset Timing
      2. 5.10.2  Input Clocks and Oscillators
        1. 5.10.2.1 Clock Specifications
      3. 5.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.10.3.1 Peripheral Description
        2. 5.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-7 SPI Timing Conditions
          2. Table 5-8 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-9 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.10.3.3 SPI Slave Mode I/O Timings
          1. Table 5-10 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 5.10.4  LVDS Interface Configuration
        1. 5.10.4.1 LVDS Interface Timings
      5. 5.10.5  General-Purpose Input/Output
        1. Table 5-12 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 5.10.6  Controller Area Network Interface (DCAN)
        1. Table 5-13 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 5.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. Table 5-14 Dynamic Characteristics for the CANx TX and RX Pins
      8. 5.10.8  Serial Communication Interface (SCI)
        1. Table 5-15 SCI Timing Requirements
      9. 5.10.9  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-16 I2C Timing Requirements
      10. 5.10.10 Quad Serial Peripheral Interface (QSPI)
        1. Table 5-17 QSPI Timing Conditions
        2. Table 5-18 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-19 QSPI Switching Characteristics
      11. 5.10.11 ETM Trace Interface
        1. Table 5-20 ETMTRACE Timing Conditions
        2. Table 5-21 ETM TRACE Switching Characteristics
      12. 5.10.12 Data Modification Module (DMM)
        1. Table 5-22 DMM Timing Requirements
      13. 5.10.13 JTAG Interface
        1. Table 5-23 JTAG Timing Conditions
        2. Table 5-24 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-25 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Processor Subsystem
      3. 6.3.3 Automotive Interface
      4. 6.3.4 Master Subsystem Cortex-R4F Memory Map
      5. 6.3.5 DSP Subsystem Memory Map
    4. 6.4 Other Subsystems
      1. 6.4.1 ADC Channels (Service) for User Application
        1. Table 6-3 GP-ADC Parameter
  7. Monitoring and Diagnostics
    1. 7.1 Monitoring and Diagnostic Mechanisms
      1. 7.1.1 Error Signaling Module
  8. Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Short- and Medium-Range Radar
    3. 8.3 Reference Schematic
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Stackup Details
  9. Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-19 QSPI Switching Characteristics

NO. PARAMETER MIN TYP MAX UNIT
Q1 tc(SCLK) Cycle time, sclk 25 ns
Q2 tw(SCLKL) Pulse duration, sclk low 0.5*P – 3(1) ns
Q3 tw(SCLKH) Pulse duration, sclk high 0.5*P – 3 ns
Q4 td(CS-SCLK) Delay time, sclk falling edge to cs active edge –M*P – 1(2) –M*P + 2.5(2) ns
Q5 td(SCLK-CS) Delay time, sclk falling edge to cs inactive edge N*P – 1(2) N*P + 2.5(2) ns
Q6 td(SCLK-D1) Delay time, sclk falling edge to d[0] transition –3.5 7 ns
Q7 tena(CS-D1LZ) Enable time, cs active edge to d[0] driven (lo-z) –P – 4(2) –P +1(2) ns
Q8 tdis(CS-D1Z) Disable time, cs active edge to d[0] tri-stated (hi-z) –P – 4(2) –P +1(2) ns
Q9 td(SCLK-D1) Delay time, sclk first falling edge to first d[1] transition (for PHA = 0 only) –3.5 – P(2) 7 – P(2) ns
P = SCLK period in ns.
M = QSPI_SPI_DC_REG.DDx + 1, N = 2
AWR1843 QSPI_read_mode0.gifFigure 5-13 QSPI Read (Clock Mode 0)
AWR1843 SPRS91v_QSPI_04.gifFigure 5-14 QSPI Write (Clock Mode 0)