SWRS222B December   2018  – April 2020 AWR1843

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
      1. Table 4-3 PAD IO Register Bit Descriptions
    3. 4.3 Signal Descriptions
      1. Table 4-4 Signal Descriptions - Digital
      2. Table 4-5 Signal Descriptions - Analog
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Power Supply Specifications
    6. 5.6  Power Consumption Summary
    7. 5.7  RF Specification
    8. 5.8  CPU Specifications
    9. 5.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 5.10 Timing and Switching Characteristics
      1. 5.10.1  Power Supply Sequencing and Reset Timing
      2. 5.10.2  Input Clocks and Oscillators
        1. 5.10.2.1 Clock Specifications
      3. 5.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.10.3.1 Peripheral Description
        2. 5.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-7 SPI Timing Conditions
          2. Table 5-8 SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-9 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.10.3.3 SPI Slave Mode I/O Timings
          1. Table 5-10 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
      4. 5.10.4  LVDS Interface Configuration
        1. 5.10.4.1 LVDS Interface Timings
      5. 5.10.5  General-Purpose Input/Output
        1. Table 5-12 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 5.10.6  Controller Area Network Interface (DCAN)
        1. Table 5-13 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 5.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. Table 5-14 Dynamic Characteristics for the CANx TX and RX Pins
      8. 5.10.8  Serial Communication Interface (SCI)
        1. Table 5-15 SCI Timing Requirements
      9. 5.10.9  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-16 I2C Timing Requirements
      10. 5.10.10 Quad Serial Peripheral Interface (QSPI)
        1. Table 5-17 QSPI Timing Conditions
        2. Table 5-18 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-19 QSPI Switching Characteristics
      11. 5.10.11 ETM Trace Interface
        1. Table 5-20 ETMTRACE Timing Conditions
        2. Table 5-21 ETM TRACE Switching Characteristics
      12. 5.10.12 Data Modification Module (DMM)
        1. Table 5-22 DMM Timing Requirements
      13. 5.10.13 JTAG Interface
        1. Table 5-23 JTAG Timing Conditions
        2. Table 5-24 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-25 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Subsystems
      1. 6.3.1 RF and Analog Subsystem
        1. 6.3.1.1 Clock Subsystem
        2. 6.3.1.2 Transmit Subsystem
        3. 6.3.1.3 Receive Subsystem
      2. 6.3.2 Processor Subsystem
      3. 6.3.3 Automotive Interface
      4. 6.3.4 Master Subsystem Cortex-R4F Memory Map
      5. 6.3.5 DSP Subsystem Memory Map
    4. 6.4 Other Subsystems
      1. 6.4.1 ADC Channels (Service) for User Application
        1. Table 6-3 GP-ADC Parameter
  7. 7 Monitoring and Diagnostics
    1. 7.1 Monitoring and Diagnostic Mechanisms
      1. 7.1.1 Error Signaling Module
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Short- and Medium-Range Radar
    3. 8.3 Reference Schematic
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Stackup Details
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABL|161
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.3 Signal Descriptions

NOTE

All digital IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being present to the device.

NOTE

The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should be used to isolate the GPIO output from the radar device and a pull resister used to define the required state in the application. The NRESET signal to the radar device could be used to control the output enable (OE) of the tri-state buffer.

Table 4-4 Signal Descriptions - Digital

SIGNAL NAME PIN TYPE DESCRIPTION BALL NO.
ADC_VALID O When high, indicating valid ADC samples H13, J13, P13
BSS_UART_TX O Debug UART Transmit [Radar Block] F14, H14, K13, N10, N13, N4, N5, R8
CAN_FD_RX I CAN FD (MCAN) Receive Signal D13, F14, N10, N4, P12
CAN_FD_TX O CAN FD (MCAN) Transmit Signal E14, H14, N5, P10, R14
CAN_RX I CAN (DCAN) Receive Signal E13
CAN_TX IO CAN (DCAN) Transmit Signal E15
CHIRP_END O Pulse signal indicating the end of each chirp K13, N8, P9
CHIRP_START O Pulse signal indicating the start of each chirp K13, N8, P9
DMM0 I Debug Interface (Hardware In Loop) - Data Line R4
DMM1 I Debug Interface (Hardware In Loop) - Data Line P5
DMM2 I Debug Interface (Hardware In Loop) - Data Line R5
DMM3 I Debug Interface (Hardware In Loop) - Data Line P6
DMM4 I Debug Interface (Hardware In Loop) - Data Line R7
DMM5 I Debug Interface (Hardware In Loop) - Data Line P7
DMM6 I Debug Interface (Hardware In Loop) - Data Line R8
DMM7 I Debug Interface (Hardware In Loop) - Data Line P8
DMM_CLK I Debug Interface (Hardware In Loop) - Clock N15
DMM_MUX_IN I Debug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances) G13, J13, P4
DMM_SYNC I Debug Interface (Hardware In Loop) - Sync N14
DSS_UART_TX O Debug UART Transmit [DSP] D13, E13, G14, P8, R12
EPWM1A O PWM Module 1 - Output A N5, N8
EPWM1B O PWM Module 1 - Output B H13, N5, P9
EPWM1SYNCI I PWM Module 1 - Sync Input J13
EPWM2A O PWM Module 2- Output A H13, N4, N5, P9
EPWM2B O PWM Module 2 - Output B N4
EPWM2SYNCO O PWM Module 2 - Sync Output R7
EPWM3A O PWM Module 3 - Output A N4
EPWM3SYNCO O PWM Module 3 - Sync Output P6
FRAME_START O Pulse signal indicating the start of each frame K13, N8, P9
GPIO_0 IO General-purpose I/O H13
GPIO_1 IO General-purpose I/O J13
GPIO_2 IO General-purpose I/O K13
GPIO_3 IO General-purpose I/O E13
GPIO_4 IO General-purpose I/O H14
GPIO_5 IO General-purpose I/O F14
GPIO_6 IO General-purpose I/O P11
GPIO_7 IO General-purpose I/O R12
GPIO_8 IO General-purpose I/O R13
GPIO_9 IO General-purpose I/O N12
GPIO_10 IO General-purpose I/O R14
GPIO_11 IO General-purpose I/O P12
GPIO_12 IO General-purpose I/O P13
GPIO_13 IO General-purpose I/O H13
GPIO_14 IO General-purpose I/O N5
GPIO_15 IO General-purpose I/O N4
GPIO_16 IO General-purpose I/O J13
GPIO_17 IO General-purpose I/O P10
GPIO_18 IO General-purpose I/O N10
GPIO_19 IO General-purpose I/O D13
GPIO_20 IO General-purpose I/O E14
GPIO_21 IO General-purpose I/O F13
GPIO_22 IO General-purpose I/O G14
GPIO_23 IO General-purpose I/O R11
GPIO_24 IO General-purpose I/O N13
GPIO_25 IO General-purpose I/O N8
GPIO_26 IO General-purpose I/O K13
GPIO_27 IO General-purpose I/O P9
GPIO_28 IO General-purpose I/O P4
GPIO_29 IO General-purpose I/O G13
GPIO_30 IO General-purpose I/O E15
GPIO_31 IO General-purpose I/O R4
GPIO_32 IO General-purpose I/O P5
GPIO_33 IO General-purpose I/O R5
GPIO_34 IO General-purpose I/O P6
GPIO_35 IO General-purpose I/O R7
GPIO_36 IO General-purpose I/O P7
GPIO_37 IO General-purpose I/O R8
GPIO_38 IO General-purpose I/O P8
GPIO_47 IO General-purpose I/O N15
I2C_SCL IO I2C Clock G14, N4
I2C_SDA IO I2C Data F13, N5
LVDS_TXP[0] O Differential data Out – Lane 0 J14
LVDS_TXM[0] O J15
LVDS_TXP[1] O Differential data Out – Lane 1 K14
LVDS_TXM[1] O K15
LVDS_CLKP O Differential clock Out L14
LVDS_CLKM O L15
LVDS_FRCLKP O Differential Frame Clock M14
LVDS_FRCLKM O M15
MCU_CLKOUT O Programmable clock given out to external MCU or the processor N8
MSS_UARTA_RX I Master Subsystem - UART A Receive F14, N4, R11
MSS_UARTA_TX O Master Subsystem - UART A Transmit H14, N13, N5, R4
MSS_UARTB_RX IO Master Subsystem - UART B Receive N4, P4
MSS_UARTB_TX O Master Subsystem - UART B Transmit F14, H14, K13, N13, N5, P10, P7
NDMM_EN I Debug Interface (Hardware In Loop) Enable - Active Low Signal N13, N5
NERROR_IN I Failsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by Firmware N7
NERROR_OUT O Open drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. N6
PMIC_CLKOUT O Output Clock from AWR1843 device for PMIC H13, K13, P9
QSPI[0] IO QSPI Data Line #0 (Used with Serial Data Flash) R13
QSPI[1] IO QSPI Data Line #1 (Used with Serial Data Flash) N12
QSPI[2] I QSPI Data Line #2 (Used with Serial Data Flash) R14
QSPI[3] IO QSPI Data Line #3 (Used with Serial Data Flash) P12
QSPI_CLK IO QSPI Clock (Used with Serial Data Flash) R12
QSPI_CLK_EXT I QSPI Clock (Used with Serial Data Flash) H14
QSPI_CS_N IO QSPI Chip Select (Used with Serial Data Flash) P11
RS232_RX I Debug UART (Operates as Bus Master) - Receive Signal N4
RS232_TX O Debug UART (Operates as Bus Master) - Transmit Signal N5
SOP[0] I Sense On Power - Line#0 N13
SOP[1] I Sense On Power - Line#1 G13
SOP[2] I Sense On Power - Line#2 P9
SPIA_CLK IO SPI Channel A - Clock E13
SPIA_CS_N IO SPI Channel A - Chip Select E15
SPIA_MISO IO SPI Channel A - Master In Slave Out E14
SPIA_MOSI IO SPI Channel A - Master Out Slave In D13
SPIB_CLK IO SPI Channel B - Clock F14, R12
SPIB_CS_N IO SPI Channel B Chip Select (Instance ID 0) H14, P11
SPIB_CS_N_1 IO SPI Channel B Chip Select (Instance ID 1) G13, J13, P13
SPIB_CS_N_2 IO SPI Channel B Chip Select (Instance ID 2) G13, J13, N12
SPIB_MISO IO SPI Channel B - Master In Slave Out G14, R13
SPIB_MOSI IO SPI Channel B - Master Out Slave In F13, N12
SPI_HOST_INTR O Out of Band Interrupt to an external host communicating over SPI P13
SYNC_IN I Low frequency Synchronization signal input P4
SYNC_OUT O Low Frequency Synchronization Signal output G13, J13, K13, P4
TCK I JTAG Test Clock P10
TDI I JTAG Test Data Input R11
TDO O JTAG Test Data Output N13
TMS I JTAG Test Mode Signal N10
TRACE_CLK O Debug Trace Output - Clock N15
TRACE_CTL O Debug Trace Output - Control N14
TRACE_DATA_0 O Debug Trace Output - Data Line R4
TRACE_DATA_1 O Debug Trace Output - Data Line P5
TRACE_DATA_2 O Debug Trace Output - Data Line R5
TRACE_DATA_3 O Debug Trace Output - Data Line P6
TRACE_DATA_4 O Debug Trace Output - Data Line R7
TRACE_DATA_5 O Debug Trace Output - Data Line P7
TRACE_DATA_6 O Debug Trace Output - Data Line R8
TRACE_DATA_7 O Debug Trace Output - Data Line P8
WARM_RESET IO Open drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset. N9

Table 4-5 Signal Descriptions - Analog

INTERFACE SIGNAL NAME PIN TYPE DESCRIPTION BALL NO.
Transmitters TX1 O Single ended transmitter1 o/p B4
TX2 O Single ended transmitter2 o/p B6
TX3 O Single ended transmitter3 o/p B8
Receivers RX1 I Single ended receiver1 i/p M2
RX2 I Single ended receiver2 i/p K2
RX3 I Single ended receiver3 i/p H2
RX4 I Single ended receiver4 i/p F2
Reset NRESET I Power on reset for chip. Active low R3
Reference Oscillator CLKP I In XTAL mode: Differential port for reference crystal
In External clock mode: Single ended input reference clock port 		B15
CLKM I In XTAL mode: Differential port for reference crystal
In External clock mode: Connect this port to ground 		C15
Reference clock OSC_CLKOUT O Reference clock output from clocking subsystem after cleanup PLL (1.4V output voltage swing). A14
Bandgap voltage VBGAP O Device's Band Gap Reference Output B10
Power supply VDDIN Power 1.2V digital power supply H15, N11, P15, R6
VIN_SRAM Power 1.2V power rail for internal SRAM G15
VNWA Power 1.2V power rail for SRAM array back bias P14
VIOIN Power I/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supply R10, F15
VIOIN_18 Power 1.8V supply for CMOS IO R9
VIN_18CLK Power 1.8V supply for clock module B11
VIOIN_18DIFF Power 1.8V supply for LVDS port D15
VPP Power Voltage supply for fuse chain L13
Power supply VIN_13RF1 Power 1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board G5, H5, J5
VIN_13RF2 Power 1.3V Analog and RF supply C2,D2
VIN_18BB Power 1.8V Analog base band power supply K5, F5
VIN_18VCO Power 1.8V RF VCO supply B12
VSS Ground Digital ground L5, L6, L8, L10, K7, K8, K9, K10, K11, J6, J7, J8, J10, H7, H9, H11, G6, G7, G8, G10, F9, F11, E5, E6, E8, E10, E11, R15
VSSA Ground Analog ground A1, A3, A5, A7, A15, B1, B3, B5, B7, C1, C3, C4, C5, C6, C7, E1, E2, E3, F3, G1, G2, G3, H3, J1, J2, J3, K3, L1, L2, L3, M3, N1, N2, N3, R1, A13, C8,A9, B9, C9, B14, C14
Internal LDO output/inputs VOUT_14APLL O Internal LDO output A10
VOUT_14SYNTH O Internal LDO output B13
VOUT_PA IO When internal PA LDO is used this pin provides the output voltage of the LDO. When the internal PA LDO is bypassed and disabled 1V supply should be fed on this pin. This is mandatory in 3TX simultaneous use case. A2, B2
Test and Debug output for pre-production phase. Can be pinned out on production hardware for field debug Analog Test1 / ADC1 IO ADC Channel 1(1) P1
Analog Test2 / ADC2 IO ADC Channel 2(1) P2
Analog Test3 / ADC3 IO ADC Channel 3(1) P3
Analog Test4 / ADC4 IO ADC Channel 4(1) R2
ANAMUX / ADC5 IO ADC Channel 5(1) C13
VSENSE / ADC6 IO ADC Channel 6(1) D14
(1) For details, see Section 6.4.1.