SLUSAN9A August   2011  – August 2015

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power-on Reset
    7. 6.7 Data Flash Characteristics Over Recommended Operating Temperature and Supply Voltage
    8. 6.8 SMBus Timing Requirements
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Feature Set
        1. 7.3.1.1 Primary (1st Level) Safety Features
        2. 7.3.1.2 Secondary (2nd Level) Safety Features
        3. 7.3.1.3 Charge Control Features
        4. 7.3.1.4 Gas Gauging
        5. 7.3.1.5 Lifetime Data Logging Features
        6. 7.3.1.6 Authentication
      2. 7.3.2 Battery Parameter Measurements
        1. 7.3.2.1 Charge and Discharge Counting
        2. 7.3.2.2 Voltage
        3. 7.3.2.3 Current
        4. 7.3.2.4 Wake Function
        5. 7.3.2.5 Auto Calibration
        6. 7.3.2.6 Temperature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
    5. 7.5 Programming
      1. 7.5.1 Configuration
        1. 7.5.1.1 Oscillator Function
        2. 7.5.1.2 System Present Operation
      2. 7.5.2 Communications
        1. 7.5.2.1 SMBus On and Off State
      3. 7.5.3 SBS Commands
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Choosing the Correct Chemistry
        2. 8.2.2.2 High-Current Path
        3. 8.2.2.3 Protection FETs
        4. 8.2.2.4 Lithium-Ion Cell Connections
        5. 8.2.2.5 Sense Resistor
        6. 8.2.2.6 ESD Mitigation
        7. 8.2.2.7 System Present
        8. 8.2.2.8 SMBus Communication
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 10.1.2 ESD Spark Gap
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout

Layout Guidelines

A battery fuel gauge circuit board is a challenging environment due to the fundamental incompatibility of high-current traces and ultra-low current semiconductor devices. The best way to protect against unwanted trace-to-trace coupling is with a component placement, such as that shown in Figure 11, where the high-current section is on the opposite side of the board from the electronic devices. Clearly this is not possible in many situations due to mechanical constraints. Still, every attempt should be made to route high-current traces away from signal traces, which enter the directly. IC references and registers can be disturbed and in rare cases damaged due to magnetic and capacitive coupling from the high-current path. During surge current and ESD events, the high-current traces appear inductive and can couple unwanted noise into sensitive nodes of the gas gauge electronics, as illustrated in Figure 12.

Kelvin voltage sensing is extremely important to accurately measure current and top and bottom cell voltages. Place all filter components as close as possible to the device. Route the traces from the sense resistor in parallel to the filter circuit. Adding a ground plane around the filter network can add additional noise immunity. Figure 7 and Figure 8 demonstrates correct kelvin current sensing.

bq20z655-R1 sens_res.gif Figure 7. Sensing Resistor PCB Layout
bq20z655-R1 FilterCircuit.gif Figure 8. Sense Resistor, Ground Shield, and Filter Circuit Layout

Protector FET Bypass and Pack Terminal Bypass Capacitors

The general principle is to use wide copper traces to lower the inductance of the bypass capacitor circuit. In Figure 9, an example layout demonstrates this technique.

bq20z655-R1 CopperTraces.gif Figure 9. Use Wide Copper Traces to Lower the Inductance of Bypass Capacitors C1, C2, and C3

ESD Spark Gap

Protect SMBus Clock, Data, and other communication lines from ESD with a spark gap at the connector. The pattern in Figure 10 recommended, with 0.2-mm spacing between the points.

bq20z655-R1 ESDSparkGap.gif Figure 10. Recommended Spark-Gap Pattern Helps Protect Communication Lines from ESD

Layout Example

bq20z655-R1 BatCircuits.gif Figure 11. Separating High- and Low-Current Sections Provides an Advantage in Noise Immunity
bq20z655-R1 signal_lines_lua392.gif Figure 12. Avoid Close Spacing Between High-Current and Low-Level Signal Lines