SLUSAN9A August   2011  – August 2015

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power-on Reset
    7. 6.7 Data Flash Characteristics Over Recommended Operating Temperature and Supply Voltage
    8. 6.8 SMBus Timing Requirements
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Feature Set
        1. 7.3.1.1 Primary (1st Level) Safety Features
        2. 7.3.1.2 Secondary (2nd Level) Safety Features
        3. 7.3.1.3 Charge Control Features
        4. 7.3.1.4 Gas Gauging
        5. 7.3.1.5 Lifetime Data Logging Features
        6. 7.3.1.6 Authentication
      2. 7.3.2 Battery Parameter Measurements
        1. 7.3.2.1 Charge and Discharge Counting
        2. 7.3.2.2 Voltage
        3. 7.3.2.3 Current
        4. 7.3.2.4 Wake Function
        5. 7.3.2.5 Auto Calibration
        6. 7.3.2.6 Temperature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
    5. 7.5 Programming
      1. 7.5.1 Configuration
        1. 7.5.1.1 Oscillator Function
        2. 7.5.1.2 System Present Operation
      2. 7.5.2 Communications
        1. 7.5.2.1 SMBus On and Off State
      3. 7.5.3 SBS Commands
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Choosing the Correct Chemistry
        2. 8.2.2.2 High-Current Path
        3. 8.2.2.3 Protection FETs
        4. 8.2.2.4 Lithium-Ion Cell Connections
        5. 8.2.2.5 Sense Resistor
        6. 8.2.2.6 ESD Mitigation
        7. 8.2.2.7 System Present
        8. 8.2.2.8 SMBus Communication
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 10.1.2 ESD Spark Gap
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

DBT Package
44-Pin TSSOP
Top View
bq20z655-R1 Pin_Out.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NO. NAME
1 DSG O High side N-chan discharge FET gate drive
2 PACK IA, P Battery pack input voltage sense input. It also serves as device wakeup when device is in shutdown mode.
3 VCC P Positive device supply input. Connect to the center connection of the CHG FET and DSG FET to ensure device supply either from battery stack or battery pack input
4 ZVCHG O P-chan pre-charge FET gate drive
5 GPOD OD High voltage general purpose open drain output. Can be configured to be used in pre-charge condition
6 PMS I Pre-charge mode setting input. Connect to PACK to enable 0-V precharge using charge FET connected at CHG pin. Connect to VSS to disable 0-V precharge using charge FET connected at CHG pin.
7 VSS P Negative supply voltage input. Connect all VSS pins together for operation of device
8 REG33 P 3.3-V regulator output. Connect at least a 2.2-μF capacitor to REG33 and VSS
9 TOUT P Thermistor bias supply output
10 VCELL+ Internal cell voltage multiplexer and amplifier output. Connect a 0.1-μF capacitor to VCELL+ and VSS
11 ALERT OD Alert output. In case of short circuit condition, overload condition and watchdog time out this pin will be triggered.
12 COM/TP Output / open drain: LCD common connection
13 TS1 IA 1st Thermistor voltage input connection to monitor temperature
14 TS2 IA 2nd Thermistor voltage input connection to monitor temperature
15 PRES I Active low input to sense system insertion. Typically requires additional ESD protection.
16 PFIN I Active low input to detect secondary protector status, and to allow the bq20z655-R1 to report the status of the 2nd level protection input.
17 SAFE OD Active high output to enforce additional level of safety protection; for example, fuse blow.
18 SMBD I/OD SMBus data open-drain bidirectional pin used to transfer address and data to and from the bq20z655-R1
19 CE A logical high on this pin only affects the normal operation on the charge FET when the battery is in charge/relax mode. For a logic low, the normal bq20z655-R1 firmware controls the charge FET.
20 SMBC I/OD SMBus clock open-drain bidirectional pin used to clock the data transfer to and from the bq20z655-R1
21 DISP I Input: In LED mode, this is the display enable input.
22 VSS P Negative supply voltage input. Connect all VSS pins together for operation of device
23 LED1/SEG1 I Output / open drain: LED 1 current sink. LCD segment 1
24 LED2/SEG2 I Output / open drain: LED 2 current sink. LCD segment 2
25 LED3/SEG3 I Output / open drain: LED 3 current sink. LCD segment 3
26 LED4/SEG4 I Output / open drain: LED 4 current sink. LCD segment 4
27 LED5/SEG5 I Output / open drain: LED 5 current sink. LCD segment 5
28 GSRP IA Coulomb counter differential input. Connect to one side of the sense resistor
29 GSRN IA Coulomb counter differential input. Connect to one side of the sense resistor
30 MRST I Master reset input that forces the device into reset when held low. Must be held high for normal operation. Connect to RESET for correct operation of device
31 VSS P Negative supply voltage input. Connect all VSS pins together for operation of device
32 REG25 P 2.5-V regulator output. Connect at least a 1-mF capacitor to REG25 and VSS
33 RBI P RAM / Register backup input. Connect a capacitor to this pin and VSS to protect loss of RAM/Register data in case of short circuit condition.
34 VSS P Negative supply voltage input. Connect all VSS pins together for operation of device
35 RESET O Reset output. Connect to MSRT.
36 ASRN IA Short circuit and overload detection differential input. Connect to sense resistor
37 ASRP IA Short circuit and overload detection differential input. Connect to sense resistor
38 VC5 IA, P Cell voltage sense input and cell balancing input for the negative voltage of the bottom cell in cell stack.
39 VC4 IA, P Cell voltage sense input and cell balancing input for the positive voltage of the bottom cell and the negative voltage of the second lowest cell in cell stack.
40 VC3 IA, P Cell voltage sense input and cell balancing input for the positive voltage of the second lowest cell in cell stack and the negative voltage of the second highest cell in 4 cell applications.
41 VC2 IA, P Cell voltage sense input and cell balancing input for the positive voltage of the second highest cell and the negative voltage of the highest cell in 4 cell applications. Connect to VC3 in 2 cell stack applications.
42 VC1 IA, P Cell voltage sense input and cell balancing input for the positive voltage of the highest cell in cell stack in 4 cell applications. Connect to VC2 in 2- or 3-stack applications.
43 BAT I, P Battery stack voltage sense input.
44 CHG O High side N-channel charge FET gate drive
I = Input, IA = Analog input, I/O = Input/output, I/OD = Input/Open-drain output, O = Output, OA = Analog output, P = Power