SLUSAN9A August   2011  – August 2015

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Power-on Reset
    7. 6.7 Data Flash Characteristics Over Recommended Operating Temperature and Supply Voltage
    8. 6.8 SMBus Timing Requirements
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Feature Set
        1. 7.3.1.1 Primary (1st Level) Safety Features
        2. 7.3.1.2 Secondary (2nd Level) Safety Features
        3. 7.3.1.3 Charge Control Features
        4. 7.3.1.4 Gas Gauging
        5. 7.3.1.5 Lifetime Data Logging Features
        6. 7.3.1.6 Authentication
      2. 7.3.2 Battery Parameter Measurements
        1. 7.3.2.1 Charge and Discharge Counting
        2. 7.3.2.2 Voltage
        3. 7.3.2.3 Current
        4. 7.3.2.4 Wake Function
        5. 7.3.2.5 Auto Calibration
        6. 7.3.2.6 Temperature
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
    5. 7.5 Programming
      1. 7.5.1 Configuration
        1. 7.5.1.1 Oscillator Function
        2. 7.5.1.2 System Present Operation
      2. 7.5.2 Communications
        1. 7.5.2.1 SMBus On and Off State
      3. 7.5.3 SBS Commands
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Choosing the Correct Chemistry
        2. 8.2.2.2 High-Current Path
        3. 8.2.2.3 Protection FETs
        4. 8.2.2.4 Lithium-Ion Cell Connections
        5. 8.2.2.5 Sense Resistor
        6. 8.2.2.6 ESD Mitigation
        7. 8.2.2.7 System Present
        8. 8.2.2.8 SMBus Communication
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
      2. 10.1.2 ESD Spark Gap
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VSS Supply voltage BAT, VCC –0.3 34 V
PACK, PMS –0.3 34
VC(n)–VC(n+1); n = 1, 2, 3, 4 –0.3 8.5
VC1, VC2, VC3, VC4 –0.3 34
VC5 –0.3 1
VIN Input voltage PFIN, SMBD, SMBC. LED1, LED2, LED3, LED4, LED5, DISP –0.3 6 V
TS1, TS2, SAFE, VCELL+, PRES, ALERT –0.3 V(REG25) + 0.3
MRST, GSRN, GSRP, RBI –0.3 V(REG25) + 0.3
ASRN, ASRP –1 1
VOUT Output voltage DSG, CHG, GPOD –0.3 34 V
ZVCHG –0.3 V(BAT)
TOUT, ALERT, REG33 –0.3 6
RESET –0.3 7
REG25 –0.3 2.75
ISS Maximum combined sink current for input pins PRES, PFIN, SMBD, SMBC, LED1, LED2, LED3, LED4, LED5 50 mA
TA Operating free-air temperature –40 85 °C
TF Functional temperature –40 100 °C
Tstg Storage temperature –65 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VSS Supply voltage VCC, BAT 4.5 25 V
V(STARTUP) Minimum start-up voltage VCC, BAT, PACK 5.5 V
VIN Input voltage VC(n)-VC(n+1); n = 1,2,3,4 0 5 V
VC1, VC2, VC3, VC4 0 VSS V
VC5 0 0.5 V
ASRN, ASRP –0.5 0.5 V
PACK, PMS 0 25 V
V(GPOD) Output voltage GPOD 0 25 V
I(GPOD) Drain current(1) GPOD 1 mA
C(REG25) 2.5-V LDO capacitor REG25 1 µF
C(REG33) 3.3-V LDO capacitor REG33 2.2 µF
C(VCELL+) Cell voltage output capacitor VCELL+ 0.1 µF
R(PACK) PACK input block resistor(2) PACK 1
Use an external resistor to limit the current to GPOD to 1 mA in high voltage application.
Use an external resistor to limit the inrush current PACK pin required.

Thermal Information

THERMAL METRIC(1) bq20z655-R1 UNIT
DBT (TSSOP)
44 PINS
RθJA Junction-to-ambient thermal resistance 60.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.3 °C/W
RθJB Junction-to-board thermal resistance 30.2 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 27.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

Electrical Characteristics

Over operating free-air temperature range, TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V, V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
I(NORMAL) Firmware running 550 µA
I(SLEEP) Sleep mode CHG FET on; DSG FET on 124 µA
CHG FET off; DSG FET on 90 µA
CHG FET off; DSG FET off 52 µA
I(SHUTDOWN) Shutdown mode 0.1 1 µA
SHUTDOWN WAKE; TA = 25°C (unless otherwise noted)
I(PACK) Shutdown exit at VSTARTUP threshold 1 µA
SRx WAKE FROM SLEEP; TA = 25°C (unless otherwise noted)
V(WAKE) Positive or negative wake threshold with 1-mV, 2.25-mV, 4.5-mV and 9-mV programmable options 1.25 10 mV
V(WAKE_ACR) Accuracy of V(WAKE) V (WAKE) = 1 mV; I(WAKE)= 0, RSNS1 = 0, RSNS0 = 1; –0.7 0.7 mV
V(WAKE) = 2.25 mV; I(WAKE) = 1, RSNS1 = 0, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0;
–0.8 0.8
V(WAKE) = 4.5 mV; I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1;
I(WAKE) = 0, RSNS1 = 1, RSNS0 = 0;
–1 1
V(WAKE) = 9 mV; I(WAKE) = 1, RSNS1 = 1, RSNS0 = 1; –1.4 1.4
V(WAKE_TCO) Temperature drift of V(WAKE) accuracy 0.5 %/°C
t(WAKE) Time from application of current and wake of bq20z655-R1 1 10 ms
WATCHDOG TIMER
tWDTINT Watchdog start-up detect time 250 500 1000 ms
tWDWT Watchdog detect time 50 100 150 µs
2.5V LDO; I(REG33OUT) = 0 mA; TA = 25°C (unless otherwise noted)
V(REG25) Regulator output voltage 4.5 < VCC or BAT < 25 V; I(REG25OUT) ≤ 16 mA;
TA = –40°C to 100°C
2.41 2.5 2.59 V
ΔV(REG25TEMP) Regulator output change with temperature I(REG25OUT) = 2 mA; TA = –40°C to 100°C ±0.2%
ΔV(REG25LINE) Line regulation 5.4 < VCC or BAT < 25 V; I(REG25OUT) = 2 mA 3 10 mV
ΔV(REG25LOAD) Load regulation 0.2 mA ≤ I(REG25OUT) ≤ 2 mA 7 25 mV
0.2 mA ≤ I(REG25OUT) ≤ 16 mA 25 50
I(REG25MAX) Current limit drawing current until
REG25 = 2 V to 0 V
5 40 75 mA
3.3V LDO; I(REG25OUT) = 0 mA; TA = 25°C (unless otherwise noted)
V(REG33) Regulator output voltage 4.5 < VCC or BAT < 25 V; I(REG33OUT) ≤ 25 mA;
TA = –40°C to 100°C
3 3.3 3.6 V
ΔV(REG33TEMP) Regulator output change with temperature I(REG33OUT) = 2 mA; TA = –40°C to 100°C ±0.2%
ΔV(REG33LINE) Line regulation 5.4 < VCC or BAT < 25 V; I(REG33OUT) = 2 mA 3 10 mV
ΔV(REG33LOAD) Load regulation 0.2 mA ≤ I(REG33OUT) ≤ 2 mA 7 17 mV
0.2 mA ≤ I(REG33OUT) ≤ 25 mA 40 100
I(REG33MAX) Current limit drawing current until REG33 = 3 V 25 100 145 mA
short REG33 to VSS, REG33 = 0 V 12 65
THERMISTOR DRIVE
V(TOUT) Output voltage I(TOUT) = 0 mA; TA = 25°C V(REG25) V
RDS(on) TOUT pass element resistance I(TOUT) = 1 mA; RDS(on) = (V(REG25) - V(TOUT) )/ 1 mA;
TA = –40°C to 100°C
50 100 Ω
LED OUTPUTS
VOL Output low voltage LED1, LED2, LED3, LED4, LED5 0.4 V
VCELL+ HIGH VOLTAGE TRANSLATION
V(VCELL+OUT) Translation output VC(n) - VC(n+1) = 0 V; TA = –40°C to 100°C 0.95 0.975 1 V
VC(n) - VC(n+1) = 4.5 V; TA = –40°C to 100°C 0.275 0.3 0.375
V(VCELL+REF) Internal AFE reference voltage ; TA = –40°C to 100°C 0.965 0.975 0.985
V(VCELL+PACK) Voltage at PACK pin; TA = –40°C to 100°C 0.98 ×
V(PACK)/18
V(PACK)/18 1.02 ×
V(PACK)/18
V(VCELL+BAT) Voltage at BAT pin; TA = –40°C to 100°C 0.98 ×
V(BAT)/18
V(BAT)/18 1.02 ×
V(BAT)/18
CMMR Common mode rejection ratio VCELL+ 40 dB
K Cell scale factor K= {VCELL+ output (VC5=0 V;
VC4=4.5 V) - VCELL+ output (VC5=0 V; VC4=0 V)}/4.5
0.147 0.15 0.153
K= {VCELL+ output (VC2=13.5 V; VC1=18 V) - VCELL+ output
(VC5=13.5 V; VC1=13.5 V)}/4.5
0.147 0.15 0.153
I(VCELL+OUT) Drive Current to VCELL+ capacitor VC(n) - VC(n+1) = 0 V; VCELL+ = 0 V; TA = –40°C to 100°C 12 18 μA
V(VCELL+O) CELL offset error CELL output (VC2 = VC1 = 18 V) - CELL output
(VC2 = VC1 = 0 V)
–18 –1 18 mV
IVCnL VC(n) pin leakage current VC1, VC2, VC3, VC4, VC5 = 3 V –1 0.01 1 μA
CELL BALANCING
RBAL internal cell balancing FET resistance RDS(on) for internal FET switch at VDS = 2 V; TA = 25°C 200 400 600 Ω
HARDWARE SHORT CIRCUIT AND OVERLOAD PROTECTION; TA = 25°C (unless otherwise noted)
V(OL) OL detection threshold voltage accuracy VOL = 25 mV (minimum) 15 25 35 mV
VOL = 100 mV; RSNS = 0, 1 90 100 110
VOL = 205 mV (maximum) 185 205 225
V(SCC) SCC detection threshold voltage accuracy V(SCC) = 50 mV (minimum) 30 50 70 mV
V(SCC) = 200 mV; RSNS = 0, 1 180 200 220
V(SCC) = 475 mV (maximum) 428 475 523
V(SCD) SCD detection threshold voltage accuracy V(SCD) = –50 mV (minimum) –30 –50 –70 mV
V(SCD) = –200 mV; RSNS = 0, 1 –180 –200 –220
V(SCD) = –475 mV (maximum) –428 –475 –523
tda Delay time accuracy ±15.25 μs
tpd Protection circuit propagation delay 50 μs
FET DRIVE CIRCUIT; TA = 25°C (unless otherwise noted)
V(DSGON) DSG pin output on voltage V(DSGON) = V(DSG) - V(PACK);
V(GS) connected to 10 MΩ; DSG and CHG on;
TA = –40°C to 100°C
8 12 16 V
V(CHGON) CHG pin output on voltage V(CHGON) = V(CHG) - V(BAT);
V(GS) = 10 MΩ; DSG and CHG on; TA = –40°C to 100°C
8 12 16 V
V(DSGOFF) DSG pin output off voltage V(DSGOFF) = V(DSG) - V(PACK) 0.2 V
V(CHGOFF) CHG pin output off voltage V(CHGOFF) = V(CHG) - V(BAT) 0.2 V
tr Rise time CL= 4700 pF V(CHG): V(PACK) ≥ V(PACK) + 4 V 400 1000 μs
V(DSG): V(BAT) ≥V(BAT) + 4 V 400 1000
tf Fall time CL= 4700 pF V(CHG): V(PACK) + V(CHGON) ≥ V(PACK)+ 1 V 40 200 μs
V(DSG): VC1 + V(DSGON) ≥ VC1 + 1 V 40 200
V(ZVCHG) ZVCHG clamp voltage BAT = 4.5 V 3.3 3.5 3.7 V
LOGIC; TA = –40°C to 100°C (unless otherwise noted)
R(PULLUP) Internal pullup resistance ALERT 60 100 200
RESET 1 3 6
VOL Logic low output voltage level ALERT 0.2 V
RESET; V(BAT) = 7 V; V(REG25) = 1.5 V; I (RESET) = 200 μA 0.4
GPOD; I(GPOD) = 50 μA 0.6
LOGIC SMBC, SMBD, PFIN, PRES, SAFE, ALERT, DISP
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
VOH Output voltage high (RC[0:7] bus) IL = –0.5 mA VREG25–0.5 V
VOL Low-level output voltage PRES, PFIN, ALERT, DISP; IL = 7 mA; 0.4 V
CI Input capacitance 5 pF
I(SAFE) SAFE source currents SAFE active, SAFE = V(REG25) –0.6 V –3 mA
Ilkg(SAFE) SAFE leakage current SAFE inactive –0.2 0.2 µA
Ilkg Input leakage current 1 µA
ADC (Unless otherwise specified, the specification limits are valid at all measurement speed modes.)
Input voltage range TS1, TS2, using Internal Vref –0.2 1 V
Conversion time 31.5 ms
Resolution (no missing codes) 16 bits
Effective resolution 14 15 bits
Integral nonlinearity ±0.03 %FSR(1)
Offset error(2) 140 250 µV
Offset error drift(2) TA = 25°C to 85°C 2.5 18 μV/°C
Full-scale error(3) ±0.1% ±0.7%
Full-scale error drift 50 PPM/°C
Effective input resistance(4) 8
COULOMB COUNTER
Input voltage range –0.20 0.20 V
Conversion time Single conversion 250 ms
Effective resolution Single conversion 15 bits
Integral nonlinearity –0.1 V to 0.2 V ±0.007 ±0.034 %FSR
–0.2 V to –0.1 V ±0.007
Offset error (5) TA = 25°C to 85°C 10 µV
Offset error drift 0.4 0.7 µV/°C
Full-scale error(6) (7) ±0.35%
Full-scale error drift 150 PPM/°C
Effective input resistance(8) TA = 25°C to 85°C 2.5
INTERNAL TEMPERATURE SENSOR
V(TEMP) Temperature sensor voltage(9) –2 mV/°C
VOLTAGE REFERENCE
Output voltage 1.215 1.225 1.230 V
Output voltage drift 65 PPM/°C
HIGH-FREQUENCY OSCILLATOR
f(OSC) Operating frequency 4.194 MHz
f(EIO) Frequency error (10) (11) –3% 0.25% 3%
TA = 20°C to 70°C –2% 0.25% 2%
t(SXO) Start-up time(12) 2.5 5 ms
LOW-FREQUENCY OSCILLATOR
f(LOSC) Operating frequency 32.768 kHz
f(LEIO) Frequency error(11) (13) –2.5% 0.25% 2.5%
TA = 20°C to 70°C –1.5% 0.25% 1.5%
t(LSXO) Start-up time(12) 500 µs
Full-scale reference
Post-calibration performance and no I/O changes during conversion with SRN as the ground reference.
Uncalibrated performance. This gain error can be eliminated with external calibration.
The A/D input is a switched-capacitor input. Because the input is switched, the effective input resistance is a measure of the average resistance.
Post-calibration performance
Reference voltage for the coulomb counter is typically Vref/3.969 at V(REG25) = 2.5 V, TA = 25°C.
Uncalibrated performance. This gain error can be eliminated with external calibration.
The CC input is a switched capacitor input. Because the input is switched, the effective input resistance is a measure of the average resistance.
–53.7 LSB/°C
The frequency error is measured from 4.194 MHz.
The frequency drift is included and measured from the trimmed frequency at V(REG25) = 2.5 V, TA = 25°C.
The start-up time is defined as the time it takes for the oscillator output frequency to be ±3%.
The frequency error is measured from 32.768 kHz.

Power-on Reset

Over operating free-air temperature range (unless otherwise noted), TA = –40°C to 85°C, V(REG25) = 2.41 V to 2.59 V,
V(BAT) = 14 V, C(REG25) = 1 µF, C(REG33) = 2.2 µF; typical values at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT– Negative-going voltage input 1.7 1.8 1.9 V
VHYS Power-on reset hysteresis 5 125 200 mV
tRST RESET active low time Active low time after power up or watchdog reset 100 250 560 µs

Data Flash Characteristics Over Recommended Operating Temperature and Supply Voltage

Typical values at TA = 25°C and V(REG25) = 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data retention See (1) 10 Years
Flash programming write-cycles 20k Cycles
t(ROWPROG) Row programming time 2 ms
t(MASSERASE) Mass-erase time 200 ms
t(PAGEERASE) Page-erase time 20 ms
I(DDPROG) Flash-write supply current 5 10 mA
I(DDERASE) Flash-erase supply current 5 10 mA
RAM/REGISTER BACKUP
I(RB) RB data-retention input current V(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 85°C 1000 2500 nA
V(RBI) > V(RBI)MIN , VREG25 < VIT–, TA = 25°C 90 220
V(RB) RB data-retention input voltage(1) 1.7 V
Specified by design. Not production tested.

SMBus Timing Requirements

TA = –40°C to 85°C Typical Values at TA = 25°C and VREG25 = 2.5 V (Unless Otherwise Noted)
MIN NOM MAX UNIT
f(SMB) SMBus operating frequency Slave mode, SMBC 50% duty cycle 10 100 kHz
f(MAS) SMBus master clock frequency Master mode, No clock low slave extend 51.2 kHz
t(BUF) Bus free time between start and stop
(see Figure 1)
4.7 µs
t(HD:STA) Hold time after (repeated) start (see Figure 1) 4 µs
t(SU:STA) Repeated start setup time (see Figure 1) 4.7 µs
t(SU:STO) Stop setup time (see Figure 1) 4 µs
t(HD:DAT) Data hold time (see Figure 1) Receive mode 0 ns
Transmit mode 300
t(SU:DAT) Data setup time (see Figure 1) 250 ns
t(TIMEOUT) Error signal/detect (see Figure 1) See (1) 25 35 µs
t(LOW) Clock low period (see Figure 1) 4.7 µs
t(HIGH) Clock high period (see Figure 1) See (2) 4 50 µs
t(LOW:SEXT) Cumulative clock low slave extend time See (3) 25 ms
t(LOW:MEXT) Cumulative clock low master extend time
(see Figure 1)
See (4) 10 ms
tf Clock/data fall time See (5) 300 ns
tr Clock/data rise time See (6) 1000 ns
The bq20z655-R1 times out when any clock low exceeds t(TIMEOUT).
t(HIGH), Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving bq20z655-R1 that is in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0).
t(LOW:SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
t(LOW:MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15)
Fall time tf = 0.9 VDD to (VILMAX – 0.15)
bq20z655-R1 smbus_tim_lus878.gif
SCLKACK is the acknowledge-related clock pulse generated by the master.
Figure 1. SMBus Timing Diagram

Typical Characteristics

bq20z655-R1 pwron2_lus878.gif Figure 2. Power On Reset Behavior vs Free-Air Temperature