SLUSDU0 September   2019 BQ21061

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Linear Charger and Power Path
        1. 7.3.1.1 Battery Charging Process
        2. 7.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 7.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
        4. 7.3.1.4 Battery Supplement Mode
      2. 7.3.2  Protection Mechanisms
        1. 7.3.2.1 Input Over-Voltage Protection
        2. 7.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 7.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 7.3.2.4 Battery Short and Over Current Protection
        5. 7.3.2.5 PMID Short Circuit
      3. 7.3.3  VDD LDO
      4. 7.3.4  Load Switch/LDO Output and Control
      5. 7.3.5  PMID Power Control
      6. 7.3.6  System Voltage (PMID) Regulation
      7. 7.3.7  MR Wake and Reset Input
        1. 7.3.7.1 MR Wake or Short Button Press Functions
        2. 7.3.7.2 MR Reset or Long Button Press Functions
      8. 7.3.8  14-Second Watchdog for HW Reset
      9. 7.3.9  Faults Conditions and Interrupts (INT)
        1. 7.3.9.1 Flags and Fault Condition Response
      10. 7.3.10 Power Good (PG) Pin
      11. 7.3.11 External NTC Monitoring (TS)
        1. 7.3.11.1 TS Thresholds
      12. 7.3.12 I2C Interface
        1. 7.3.12.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ship Mode
      2. 7.4.2 Low Power
      3. 7.4.3 Active Battery
      4. 7.4.4 Charger/Adapter Mode
      5. 7.4.5 Power-Up/Down Sequencing
    5. 7.5 Register Map
      1. 7.5.1 I2C Registers
        1. 7.5.1.1  STAT0 Register (Address = 0x0) [reset = X]
          1. Table 8. STAT0 Register Field Descriptions
        2. 7.5.1.2  STAT1 Register (Address = 0x1) [reset = X]
          1. Table 9. STAT1 Register Field Descriptions
        3. 7.5.1.3  STAT2 Register (Address = 0x2) [reset = X]
          1. Table 10. STAT2 Register Field Descriptions
        4. 7.5.1.4  FLAG0 Register (Address = 0x3) [reset = 0x0]
          1. Table 11. FLAG0 Register Field Descriptions
        5. 7.5.1.5  FLAG1 Register (Address = 0x4) [reset = 0x0]
          1. Table 12. FLAG1 Register Field Descriptions
        6. 7.5.1.6  FLAG2 Register (Address = 0x5) [reset = 0x0]
          1. Table 13. FLAG2 Register Field Descriptions
        7. 7.5.1.7  FLAG3 Register (Address = 0x6) [reset = 0x0]
          1. Table 14. FLAG3 Register Field Descriptions
        8. 7.5.1.8  MASK0 Register (Address = 0x7) [reset = 0x0]
          1. Table 15. MASK0 Register Field Descriptions
        9. 7.5.1.9  MASK1 Register (Address = 0x8) [reset = 0x0]
          1. Table 16. MASK1 Register Field Descriptions
        10. 7.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]
          1. Table 17. MASK2 Register Field Descriptions
        11. 7.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]
          1. Table 18. MASK3 Register Field Descriptions
        12. 7.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]
          1. Table 19. VBAT_CTRL Register Field Descriptions
        13. 7.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x8]
          1. Table 20. ICHG_CTRL Register Field Descriptions
        14. 7.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x2]
          1. Table 21. PCHRGCTRL Register Field Descriptions
        15. 7.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]
          1. Table 22. TERMCTRL Register Field Descriptions
        16. 7.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x0]
          1. Table 23. BUVLO Register Field Descriptions
        17. 7.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x82]
          1. Table 24. CHARGERCTRL0 Register Field Descriptions
        18. 7.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0xC2]
          1. Table 25. CHARGERCTRL1 Register Field Descriptions
        19. 7.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x6]
          1. Table 26. ILIMCTRL Register Field Descriptions
        20. 7.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0xB0]
          1. Table 27. LDOCTRL Register Field Descriptions
        21. 7.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2A]
          1. Table 28. MRCTRL Register Field Descriptions
        22. 7.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x10]
          1. Table 29. ICCTRL0 Register Field Descriptions
        23. 7.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]
          1. Table 30. ICCTRL1 Register Field Descriptions
        24. 7.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x40]
          1. Table 31. ICCTRL2 Register Field Descriptions
        25. 7.5.1.25 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]
          1. Table 32. TS_FASTCHGCTRL Register Field Descriptions
        26. 7.5.1.26 TS_COLD Register (Address = 0x62) [reset = 0x7C]
          1. Table 33. TS_COLD Register Field Descriptions
        27. 7.5.1.27 TS_COOL Register (Address = 0x63) [reset = 0x6D]
          1. Table 34. TS_COOL Register Field Descriptions
        28. 7.5.1.28 TS_WARM Register (Address = 0x64) [reset = 0x38]
          1. Table 35. TS_WARM Register Field Descriptions
        29. 7.5.1.29 TS_HOT Register (Address = 0x65) [reset = 0x27]
          1. Table 36. TS_HOT Register Field Descriptions
        30. 7.5.1.30 DEVICE_ID Register (Address = 0x6F) [reset = 0x3A]
          1. Table 37. DEVICE_ID Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input (IN/PMID) Capacitors
        2. 8.2.2.2 VDD, LDO Input and Output Capacitors
        3. 8.2.2.3 TS
        4. 8.2.2.4 Recommended Passive Components
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

VIN = 5V, VBAT = 3.6V. TJ = 25°C unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CURRENTS
IIN Input supply current PMID_MODE = 01, VIN = 5V, VBAT = 3.6V 500 µA
VIN = 5V, VBAT = 3.6V Charge Disabled 1.6 mA
IBAT_SHIP Battery Discharge Current in Ship Mode VIN = 0V , VBAT = 3.6V 10 nA
IBAT_LP Battery Quiescent Current in Low-power Mode VIN = 0V , VBAT = 3.6V, LDO Disabled 0.46 0.9 µA
VIN = 0V , VBAT = 3.6V, LDO Enabled 1.7 1.9 µA
IBAT_ACTIVE Battery Quiescent Current in Active Mode VIN = 0V , VBAT = 3.6V, LDO Disabled 18 23 µA
VIN = 0V , VBAT = 3.6V, LDO Enabled 21 25 µA
POWER PATH MANAGEMENT AND INPUT CURRENT LIMIT
VPMID_REG Default System (PMID) Regulation Voltage 4.5 V
VPMID_REG_ACC System Regulation Voltage Accuracy VIN = 5V, VPMID_REG = 4.5V. IPMID = 100mA, TJ = 25°C -1 1 %
VIN = 5V, VPMID_REG = 4.5V. IPMID = 0- 500mA –3 3 %
RON(IN-PMID) Input FET ON resistance IILIM = 500mA (ILIM = 110), VIN = 5V, IIN = 150mA 280 520
VBSUP1 Enter supplements mode threshold VBAT > VBATUVLO, DPPM enabled or Charge disabled VPMID < VBAT – 40mV mV
VBSUP2 Exit supplements mode threshold VBAT > VBATUVLO, DPPM enabled or Charge disabled VPMID < VBAT – 20mV mV
IILIM Input Current Limit Programmable Range 50 600 mA
IILIM = 50mA 45 50 mA
IILIM = 100mA 90 100 mA
IILIM = 150mA 135 150 mA
IILIM = 500mA 450 500 mA
VIN_DPM Input DPM voltage threshold where current in reduced Programmable Range 4.2 4.9 V
Accuracy –3 3 %
BATTERY CHARGER
VDPPM PMID voltage threshold when charge current is reduced VPMID - VBAT 200 mV
RON(BAT-PMID) Battery Discharge FET On Resistance VBAT = 4.35V, IBAT = 100mA 100 175
VBATREG Charge Voltage Programmable charge voltage range 3.6 4.6 V
Voltage Regulation Accuracy 0.5 0.5 %
ICHARGE Fast Charge Programmable Current Range VLOWV < VBAT < VBATREG 1.25 500 mA
Fast Charge Current Accuracy ICHARGE > 5mA –5 5 %
IPRECHARGE Precharge current Precharge current programmable range 1.25 77.5 mA
Precharge Current Accuracy -40°C < TJ < 85°C –10 10 %
ITERM Termination Charge Current Termination Current Programmable Range 1 31 %
Accuracy ITERM = 10% ICHARGE, ICHARGE = 100mA –5(1) 5(1) %
VLOWV Programmable voltage threshold for pre-charge to fast charge transitions VBAT rising. Programmable Range 2.8 3 V
VSHORT Battery voltage threshold for short detection VBAT falling, VIN = 5V 2.41 2.54 2.67 V
ISHORT Charge Current in Battery Short Condition VBAT < VSHORT IPRECHARGE mA
VRCH Recharge Threshold voltage VBAT falling, VBATREG = 4.2V, VRCH = 140mV setting 140 mV
VBAT falling, VBATREG = 4.2V, VRCH = 200mV setting 200 mV
RPMID_PD PMID pull-down resistance VPMID = 3.6V 25 Ω
VDD
VDD VDD LDO output voltage 1.8 V
LS/LDO
VINLS Input voltage range for Load switch Mode 0.8 5.5 V
Input voltage range for LDO Mode 2.2 or VLDO + 500mV 5.5 V
VLDO LDO programmable output voltage range 0.6 3.7 V
LDO output accuracy TJ = 25°C –2 2 %
VLDO = 1.8V, VINLS =3.6V. ILOAD = 1mA –3 3 %
ΔVOUT/ΔIOUT DC Load Regulation 0°C < TJ < 85°C, 1 mA < IOUT < 150mA, VLDO = 1.8V 1.2 %
ΔVOUT/ΔVIN DC Line Regulation 0°C < TJ < 85°C, Over VINLS range, IOUT = 100mA, VLDO = 1.8V 0.5 %
RDOSN_LDO Switch On resistance VINLS = 3.6V 250 450
RDSCH_LSLDO Discharge FET On-resistance for LS VINLS = 3.6V 40 Ω
IOCL_LDO Output Current Limit VLS/LDO = 0V 200 300 mA
IIN_LDO LDO VINLS quiescent current in LDO mode VBAT = VINLS=3.6V 0.9 µA
OFF State Supply Current VBAT = VINLS=3.6V 0.25 µA
BATTERY PACK NTC MONITOR
VHOT High temperature threshold VTS falling, -10°C < TJ < 85°C 0.182(1) 0.185 0.189(1) V
VWARM Warm temperature threshold VTS falling, -10°C < TJ < 85°C 0.262(1) 0.265 0.268(1) V
VCOOL Cool temperature threshold VTS rising, -10°C < TJ < 85°C 0.510(1) 0.514 0.518(1) V
VCOLD Cold temperature threshold VTS rising, -10°C < TJ < 85°C 0.581(1) 0.585 0.589(1) V
VOPEN TS Open threshold VTS rising, -10°C < TJ < 85°C 0.9 V
VHYS Threshold hysteresis 4.7 mV
ITS_BIAS TS bias current -10°C < TJ < 85°C 78.4 80 81.6 µA
PROTECTION
VUVLO IN active threshold voltage VIN rising 3.4 V
VIN falling 3.25 V
VBATUVLO Battery undervoltage Lockout Threshold Voltage Programmable range, 150 mV Hysteresis 2.4 3 V
Accuracy –3 3 %
Battery undervoltage Lockout Threshold Voltage at Power Up VBAT rising, VIN = 0V, TJ = 25°C 3.15 V
VSLP_ENTRY Sleep Entry Threshold (VIN - VBAT) 2.0V < VBAT < VBATREG, VIN falling 80 mV
VSLP_EXIT Sleep Exit Threshold (VIN - VBAT) 2.0V < VBAT < VBATREG 130 mV
VOVP Input Supply Over Voltage Threshold VIN rising 5.35 5.5 5.8 V
VIN falling (125mV hysteresis) 5.4 V
IBAT_OCP Battery Over Current Threshold Programmable range IBAT_OCP increasing 1200 1600 mA
Current Limit Accuracy –30 30 %
TSHUTDOWN Thermal shutdown trip point 125 °C
THYS Thermal shutdown trip point hysteresis 15 °C
I2C INTERFACE (SCL and SDA)
I2C Frequency 100 400 kHz
VIL Input Low threshold level VPULLUP = VIO = 1.8V 0.25 * VIO V
VIH Input High Threshold level VPULLUP = VIO = 1.8V 0.75 * VIO V
VOL Output Low threshold level VPULLUP = VIO = 1.8V, ILOAD = 5mA 0.25 * VIO V
ILKG High-level leakage Current VPULLUP = VIO = 1.8V 1 µA
/MR INPUT
RPU Internal pull up resistance 90 125 170
VIL /MR Input Low threshold level VBAT > VBUVLO 0.3 V
/INT, /PG OUTPUTS
VOL Output Low threshold level VPULLUP = VIO = 1.8V, ILOAD = 5mA 0.25 * VIO V
ILKG /INT Hi level leakage Current High Impedance, VPULLUP = VIO = 1.8V 1 µA
/CE, /LP INPUTS
RPDOWN /CE pull down resistance 900
VIL Input Low threshold level VIO = 1.8V 0.45 V
VIH /CE Input High Threshold level VIO = 1.8V 1.35 V
Based on Characterization Data