SLUSDU0 September   2019 BQ21061

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Linear Charger and Power Path
        1. 7.3.1.1 Battery Charging Process
        2. 7.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 7.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
        4. 7.3.1.4 Battery Supplement Mode
      2. 7.3.2  Protection Mechanisms
        1. 7.3.2.1 Input Over-Voltage Protection
        2. 7.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 7.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 7.3.2.4 Battery Short and Over Current Protection
        5. 7.3.2.5 PMID Short Circuit
      3. 7.3.3  VDD LDO
      4. 7.3.4  Load Switch/LDO Output and Control
      5. 7.3.5  PMID Power Control
      6. 7.3.6  System Voltage (PMID) Regulation
      7. 7.3.7  MR Wake and Reset Input
        1. 7.3.7.1 MR Wake or Short Button Press Functions
        2. 7.3.7.2 MR Reset or Long Button Press Functions
      8. 7.3.8  14-Second Watchdog for HW Reset
      9. 7.3.9  Faults Conditions and Interrupts (INT)
        1. 7.3.9.1 Flags and Fault Condition Response
      10. 7.3.10 Power Good (PG) Pin
      11. 7.3.11 External NTC Monitoring (TS)
        1. 7.3.11.1 TS Thresholds
      12. 7.3.12 I2C Interface
        1. 7.3.12.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ship Mode
      2. 7.4.2 Low Power
      3. 7.4.3 Active Battery
      4. 7.4.4 Charger/Adapter Mode
      5. 7.4.5 Power-Up/Down Sequencing
    5. 7.5 Register Map
      1. 7.5.1 I2C Registers
        1. 7.5.1.1  STAT0 Register (Address = 0x0) [reset = X]
          1. Table 8. STAT0 Register Field Descriptions
        2. 7.5.1.2  STAT1 Register (Address = 0x1) [reset = X]
          1. Table 9. STAT1 Register Field Descriptions
        3. 7.5.1.3  STAT2 Register (Address = 0x2) [reset = X]
          1. Table 10. STAT2 Register Field Descriptions
        4. 7.5.1.4  FLAG0 Register (Address = 0x3) [reset = 0x0]
          1. Table 11. FLAG0 Register Field Descriptions
        5. 7.5.1.5  FLAG1 Register (Address = 0x4) [reset = 0x0]
          1. Table 12. FLAG1 Register Field Descriptions
        6. 7.5.1.6  FLAG2 Register (Address = 0x5) [reset = 0x0]
          1. Table 13. FLAG2 Register Field Descriptions
        7. 7.5.1.7  FLAG3 Register (Address = 0x6) [reset = 0x0]
          1. Table 14. FLAG3 Register Field Descriptions
        8. 7.5.1.8  MASK0 Register (Address = 0x7) [reset = 0x0]
          1. Table 15. MASK0 Register Field Descriptions
        9. 7.5.1.9  MASK1 Register (Address = 0x8) [reset = 0x0]
          1. Table 16. MASK1 Register Field Descriptions
        10. 7.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]
          1. Table 17. MASK2 Register Field Descriptions
        11. 7.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]
          1. Table 18. MASK3 Register Field Descriptions
        12. 7.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]
          1. Table 19. VBAT_CTRL Register Field Descriptions
        13. 7.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x8]
          1. Table 20. ICHG_CTRL Register Field Descriptions
        14. 7.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x2]
          1. Table 21. PCHRGCTRL Register Field Descriptions
        15. 7.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]
          1. Table 22. TERMCTRL Register Field Descriptions
        16. 7.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x0]
          1. Table 23. BUVLO Register Field Descriptions
        17. 7.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x82]
          1. Table 24. CHARGERCTRL0 Register Field Descriptions
        18. 7.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0xC2]
          1. Table 25. CHARGERCTRL1 Register Field Descriptions
        19. 7.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x6]
          1. Table 26. ILIMCTRL Register Field Descriptions
        20. 7.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0xB0]
          1. Table 27. LDOCTRL Register Field Descriptions
        21. 7.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2A]
          1. Table 28. MRCTRL Register Field Descriptions
        22. 7.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x10]
          1. Table 29. ICCTRL0 Register Field Descriptions
        23. 7.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]
          1. Table 30. ICCTRL1 Register Field Descriptions
        24. 7.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x40]
          1. Table 31. ICCTRL2 Register Field Descriptions
        25. 7.5.1.25 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]
          1. Table 32. TS_FASTCHGCTRL Register Field Descriptions
        26. 7.5.1.26 TS_COLD Register (Address = 0x62) [reset = 0x7C]
          1. Table 33. TS_COLD Register Field Descriptions
        27. 7.5.1.27 TS_COOL Register (Address = 0x63) [reset = 0x6D]
          1. Table 34. TS_COOL Register Field Descriptions
        28. 7.5.1.28 TS_WARM Register (Address = 0x64) [reset = 0x38]
          1. Table 35. TS_WARM Register Field Descriptions
        29. 7.5.1.29 TS_HOT Register (Address = 0x65) [reset = 0x27]
          1. Table 36. TS_HOT Register Field Descriptions
        30. 7.5.1.30 DEVICE_ID Register (Address = 0x6F) [reset = 0x3A]
          1. Table 37. DEVICE_ID Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input (IN/PMID) Capacitors
        2. 8.2.2.2 VDD, LDO Input and Output Capacitors
        3. 8.2.2.3 TS
        4. 8.2.2.4 Recommended Passive Components
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 24. All I2C-compatible devices should recognize a start condition.

BQ21061 start_stop_lusba2.gifFigure 24. START and STOP Condition

The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 25). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 26) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established.

BQ21061 serial_inf_lusba2.gifFigure 25. Bit Transfer on the Serial Interface

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 24). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in this section will result in FFh being read out.

BQ21061 i2c_bus_lusba2.gifFigure 26. Acknowledge on the I2C Bus
BQ21061 bus_proto_lusba2.gifFigure 27. Bus Protocol