SLUSDU0 September 2019 BQ21061
The BQ21061 device uses a fully compliant I2C interface to program and read control parameters, status bits, and so on. I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a micro-controller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.
The BQ21061 works as a slave and supports the following data transfer modes, as defined in the I2C Bus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements.
Register contents remain intact as long as VBAT or VIN voltages remains above their respective UVLO levels.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The BQ21061 device 7-bit address is 0×6B (shifted 8-bit address is 0xD6).