SLUSDU0 September   2019 BQ21061

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Linear Charger and Power Path
        1. 7.3.1.1 Battery Charging Process
        2. 7.3.1.2 JEITA and Battery Temperature Dependent Charging
        3. 7.3.1.3 Input Voltage Based Dynamic Power Management (VINDPM) and Dynamic Power Path Management (DPPM)
        4. 7.3.1.4 Battery Supplement Mode
      2. 7.3.2  Protection Mechanisms
        1. 7.3.2.1 Input Over-Voltage Protection
        2. 7.3.2.2 Safety Timer and I2C Watchdog Timer
        3. 7.3.2.3 Thermal Protection and Thermal Charge Current Foldback
        4. 7.3.2.4 Battery Short and Over Current Protection
        5. 7.3.2.5 PMID Short Circuit
      3. 7.3.3  VDD LDO
      4. 7.3.4  Load Switch/LDO Output and Control
      5. 7.3.5  PMID Power Control
      6. 7.3.6  System Voltage (PMID) Regulation
      7. 7.3.7  MR Wake and Reset Input
        1. 7.3.7.1 MR Wake or Short Button Press Functions
        2. 7.3.7.2 MR Reset or Long Button Press Functions
      8. 7.3.8  14-Second Watchdog for HW Reset
      9. 7.3.9  Faults Conditions and Interrupts (INT)
        1. 7.3.9.1 Flags and Fault Condition Response
      10. 7.3.10 Power Good (PG) Pin
      11. 7.3.11 External NTC Monitoring (TS)
        1. 7.3.11.1 TS Thresholds
      12. 7.3.12 I2C Interface
        1. 7.3.12.1 F/S Mode Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 Ship Mode
      2. 7.4.2 Low Power
      3. 7.4.3 Active Battery
      4. 7.4.4 Charger/Adapter Mode
      5. 7.4.5 Power-Up/Down Sequencing
    5. 7.5 Register Map
      1. 7.5.1 I2C Registers
        1. 7.5.1.1  STAT0 Register (Address = 0x0) [reset = X]
          1. Table 8. STAT0 Register Field Descriptions
        2. 7.5.1.2  STAT1 Register (Address = 0x1) [reset = X]
          1. Table 9. STAT1 Register Field Descriptions
        3. 7.5.1.3  STAT2 Register (Address = 0x2) [reset = X]
          1. Table 10. STAT2 Register Field Descriptions
        4. 7.5.1.4  FLAG0 Register (Address = 0x3) [reset = 0x0]
          1. Table 11. FLAG0 Register Field Descriptions
        5. 7.5.1.5  FLAG1 Register (Address = 0x4) [reset = 0x0]
          1. Table 12. FLAG1 Register Field Descriptions
        6. 7.5.1.6  FLAG2 Register (Address = 0x5) [reset = 0x0]
          1. Table 13. FLAG2 Register Field Descriptions
        7. 7.5.1.7  FLAG3 Register (Address = 0x6) [reset = 0x0]
          1. Table 14. FLAG3 Register Field Descriptions
        8. 7.5.1.8  MASK0 Register (Address = 0x7) [reset = 0x0]
          1. Table 15. MASK0 Register Field Descriptions
        9. 7.5.1.9  MASK1 Register (Address = 0x8) [reset = 0x0]
          1. Table 16. MASK1 Register Field Descriptions
        10. 7.5.1.10 MASK2 Register (Address = 0x9) [reset = 0x71]
          1. Table 17. MASK2 Register Field Descriptions
        11. 7.5.1.11 MASK3 Register (Address = 0xA) [reset = 0x0]
          1. Table 18. MASK3 Register Field Descriptions
        12. 7.5.1.12 VBAT_CTRL Register (Address = 0x12) [reset = 0x3C]
          1. Table 19. VBAT_CTRL Register Field Descriptions
        13. 7.5.1.13 ICHG_CTRL Register (Address = 0x13) [reset = 0x8]
          1. Table 20. ICHG_CTRL Register Field Descriptions
        14. 7.5.1.14 PCHRGCTRL Register (Address = 0x14) [reset = 0x2]
          1. Table 21. PCHRGCTRL Register Field Descriptions
        15. 7.5.1.15 TERMCTRL Register (Address = 0x15) [reset = 0x14]
          1. Table 22. TERMCTRL Register Field Descriptions
        16. 7.5.1.16 BUVLO Register (Address = 0x16) [reset = 0x0]
          1. Table 23. BUVLO Register Field Descriptions
        17. 7.5.1.17 CHARGERCTRL0 Register (Address = 0x17) [reset = 0x82]
          1. Table 24. CHARGERCTRL0 Register Field Descriptions
        18. 7.5.1.18 CHARGERCTRL1 Register (Address = 0x18) [reset = 0xC2]
          1. Table 25. CHARGERCTRL1 Register Field Descriptions
        19. 7.5.1.19 ILIMCTRL Register (Address = 0x19) [reset = 0x6]
          1. Table 26. ILIMCTRL Register Field Descriptions
        20. 7.5.1.20 LDOCTRL Register (Address = 0x1D) [reset = 0xB0]
          1. Table 27. LDOCTRL Register Field Descriptions
        21. 7.5.1.21 MRCTRL Register (Address = 0x30) [reset = 0x2A]
          1. Table 28. MRCTRL Register Field Descriptions
        22. 7.5.1.22 ICCTRL0 Register (Address = 0x35) [reset = 0x10]
          1. Table 29. ICCTRL0 Register Field Descriptions
        23. 7.5.1.23 ICCTRL1 Register (Address = 0x36) [reset = 0x0]
          1. Table 30. ICCTRL1 Register Field Descriptions
        24. 7.5.1.24 ICCTRL2 Register (Address = 0x37) [reset = 0x40]
          1. Table 31. ICCTRL2 Register Field Descriptions
        25. 7.5.1.25 TS_FASTCHGCTRL Register (Address = 0x61) [reset = 0x34]
          1. Table 32. TS_FASTCHGCTRL Register Field Descriptions
        26. 7.5.1.26 TS_COLD Register (Address = 0x62) [reset = 0x7C]
          1. Table 33. TS_COLD Register Field Descriptions
        27. 7.5.1.27 TS_COOL Register (Address = 0x63) [reset = 0x6D]
          1. Table 34. TS_COOL Register Field Descriptions
        28. 7.5.1.28 TS_WARM Register (Address = 0x64) [reset = 0x38]
          1. Table 35. TS_WARM Register Field Descriptions
        29. 7.5.1.29 TS_HOT Register (Address = 0x65) [reset = 0x27]
          1. Table 36. TS_HOT Register Field Descriptions
        30. 7.5.1.30 DEVICE_ID Register (Address = 0x6F) [reset = 0x3A]
          1. Table 37. DEVICE_ID Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input (IN/PMID) Capacitors
        2. 8.2.2.2 VDD, LDO Input and Output Capacitors
        3. 8.2.2.3 TS
        4. 8.2.2.4 Recommended Passive Components
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

I2C Interface

The BQ21061 device uses a fully compliant I2C interface to program and read control parameters, status bits, and so on. I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a micro-controller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device.

The BQ21061 works as a slave and supports the following data transfer modes, as defined in the I2C Bus Specification: standard mode (100 kbps) and fast mode (400 kbps). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements.

Register contents remain intact as long as VBAT or VIN voltages remains above their respective UVLO levels.

The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-mode in this document. The BQ21061 device 7-bit address is 0×6B (shifted 8-bit address is 0xD6).