SLUSBP6C September   2013  – December 2016

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Power Up
        1. 9.3.1.1 Power-On-Reset (POR)
        2. 9.3.1.2 Power Up from Battery without DC Source
          1. 9.3.1.2.1 BATFET Turn Off
          2. 9.3.1.2.2 Shipping Mode
        3. 9.3.1.3 Power Up from DC Source
          1. 9.3.1.3.1 REGN LDO
          2. 9.3.1.3.2 Input Source Qualification
          3. 9.3.1.3.3 Input Current Limit Detection
          4. 9.3.1.3.4 D+/D- Detection Sets Input Current Limit (bq24297)
          5. 9.3.1.3.5 PSEL/OTG Pins Set Input Current Limit
          6. 9.3.1.3.6 HIZ State with 100mA USB Host
          7. 9.3.1.3.7 Force Input Current Limit Detection
        4. 9.3.1.4 Converter Power-Up
        5. 9.3.1.5 Boost Mode Operation from Battery
      2. 9.3.2 Power Path Management
        1. 9.3.2.1 Narrow VDC Architecture
        2. 9.3.2.2 Dynamic Power Management
        3. 9.3.2.3 Supplement Mode
      3. 9.3.3 Battery Charging Management
        1. 9.3.3.1 Autonomous Charging Cycle
        2. 9.3.3.2 Battery Charging Profile
        3. 9.3.3.3 Thermistor Qualification
          1. 9.3.3.3.1 Cold/Hot Temperature Window
        4. 9.3.3.4 Charging Termination
          1. 9.3.3.4.1 Termination When REG02[0] = 1
        5. 9.3.3.5 Charging Safety Timer
          1. 9.3.3.5.1 Safety Timer Configuration Change
        6. 9.3.3.6 USB Timer When Charging from USB100mA Source
      4. 9.3.4 Status Outputs (PG, STAT, and INT)
        1. 9.3.4.1 Power Good Indicator (PG) (bq24296)
        2. 9.3.4.2 Charging Status Indicator (STAT)
        3. 9.3.4.3 Interrupt to Host (INT)
      5. 9.3.5 Protections
        1. 9.3.5.1 Input Current Limit on ILIM
        2. 9.3.5.2 Thermal Regulation and Thermal Shutdown
        3. 9.3.5.3 Voltage and Current Monitoring in Buck Mode
          1. 9.3.5.3.1 Input Over-Voltage (ACOV)
          2. 9.3.5.3.2 System Over-Voltage Protection (SYSOVP)
        4. 9.3.5.4 Voltage and Current Monitoring in Boost Mode
          1. 9.3.5.4.1 Over-Current Protection
          2. 9.3.5.4.2 VBUS Over-Voltage Protection
        5. 9.3.5.5 Battery Protection
          1. 9.3.5.5.1 Battery Over-Voltage Protection (BATOVP)
          2. 9.3.5.5.2 Battery Short Protection
          3. 9.3.5.5.3 System Over-Current Protection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Host Mode and Default Mode
        1. 9.4.1.1 Plug in USB100mA Source with Good Battery
        2. 9.4.1.2 USB Timer When Charging from USB100mA Source
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Data Validity
        2. 9.5.1.2 START and STOP Conditions
        3. 9.5.1.3 Byte Format
        4. 9.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 9.5.1.5 Slave Address and Data Direction Bit
          1. 9.5.1.5.1 Single Read and Write
          2. 9.5.1.5.2 Multi-Read and Multi-Write
    6. 9.6 Register Map
      1. 9.6.1 I2C Registers
        1. 9.6.1.1  Input Source Control Register REG00 [reset = 00110xxx, or 3x]
        2. 9.6.1.2  Power-On Configuration Register REG01 [reset = 00011011, or 0x1B]
        3. 9.6.1.3  Charge Current Control Register REG02 [reset = 01100000, or 60]
        4. 9.6.1.4  Pre-Charge/Termination Current Control Register REG03 [reset = 00010001, or 0x11]
        5. 9.6.1.5  Charge Voltage Control Register REG04 [reset = 10110010, or 0xB2]
        6. 9.6.1.6  Charge Termination/Timer Control Register REG05 [reset = 10011010, or 0x9A]
        7. 9.6.1.7  Boost Voltage/Thermal Regulation Control Register REG06 [reset = 01110011, or 0x73]
        8. 9.6.1.8  Misc Operation Control Register REG07 [reset = 01001011, or 4B]
        9. 9.6.1.9  System Status Register REG08
        10. 9.6.1.10 New Fault Register REG09
        11. 9.6.1.11 Vender / Part / Revision Status Register REG0A
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Inductor Selection
        2. 10.2.2.2 Input Capacitor
        3. 10.2.2.3 Output Capacitor
      3. 10.2.3 Application Performance Plots
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description

Overview

The bq24296, bq24297 is an I2C controlled power path management device and a single cell Li-Ion battery charger. It integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. The device also integrates the bootstrap diode for the high-side gate drive.

Functional Block Diagram

bq24296 bq24297 fbd_lusbp6.gif

Feature Description

Device Power Up

Power-On-Reset (POR)

The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.

Power Up from Battery without DC Source

If only battery is present and the voltage is above depletion threshold (VBAT_DEPL), the BATFET turns on and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDSON in BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. During both boost and charge mode, the device always monitors the discharge current through BATFET. When the system is overloaded or shorted, the device will immediately turn off BATFET and keep BATFET off until the input source plugs in again.

BATFET Turn Off

The BATFET can be forced off by the host through I2C REG07[5]. This bit allows the user to independently turn off the BATFET when the battery condition becomes abnormal during charging. When BATFET is off, there is no path to charge or discharge the battery. When battery is not attached, the BATFET should be turned off by setting REG07[5] to 1 to disable charging and supplement mode.

Shipping Mode

To extend battery life and minimize power when system is powered off during system idle, shipping, or storage, the device can turn off BATFET so that the system voltage is zero to minimize the leakage. The BATFET can be turned off by setting REG07[5] (BATFET_DISABLE) bit.

In order to keep BATFET off during shipping mode, the host has to disable the watchdog timer (REG05[5:4] = 00) and disable BATFET (REG07[5] = 1) at the same time. Once the BATFET is disabled, one of the following events can turn on BATFET and clear REG07[5] (BATFET_DISABLE) bit.

  1. Plug in adapter
  2. Write REG07[5] = 0
  3. watchdog timer expiration
  4. Register reset (REG01[7] = 1)
  5. A logic low to high transition on QON pin (refer to Figure 11 for detail timing)
bq24296 bq24297 QON_timing_lusbc1.gif Figure 11. QON Timing

Power Up from DC Source

When the DC source plugs in, the charger device checks the input source voltage to turn on REGN LDO and all the bias circuits. It also checks the input current limit before starts the buck converter.

REGN LDO

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also provides bias rail to TS external resistors. The pull-up rail of STAT and PG (bq24296) can be connected to REGN as well.

The REGN is enabled when all the conditions are valid.

  1. VBUS above VVBUS_UVLOZ
  2. VBUS above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode
  3. After typical 220-ms delay (100 ms minimum) is complete

If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than IVBUS (15 µA typical) from VBUS during HIZ state. The battery powers up the system when the device is in HIZ.

Input Source Qualification

After REGN LDO powers up, the device checks the current capability of the input source. The input source has to meet the following requirements to start the buck converter.

  1. VBUS voltage below VACOV (not in VBUS over-voltage)
  2. VBUS voltage above VBADSRC (3.8 V typical) when pulling IBADSRC (30 mA typical) (poor source detection)

Once the input source passes all the conditions above, the status register REG08[2] goes high and the PG pin (bq24296) goes low. An INT is asserted to the host.

If the device fails the poor source detection, it will repeat the detection every 2 seconds.

Input Current Limit Detection

The USB ports on personal computers are convenient charging source for portable devices (PDs). If the portable device is attached to a USB host, the USB specification requires the portable device to draw limited current (100 mA/500 mA in USB 2.0, and 150 mA/900 mA in USB 3.0). If the portable device is attached to a charging port, it is allowed to draw up to 3 A.

After the PG is LOW (bq24296) or REG08[2] goes HIGH, the charger device always runs input current limit detection when a DC source plugs in unless the charger is in HIZ during host mode.

The bq24297 follows Battery Charging Specification 1.2 (BC1.2) to detect input source through USB D+/D- lines. The bq24296 sets input current limit through PSEL and OTG pins. After the input current limit detection is done, the detection result is reported in VBUS_STAT registers (REG08[7:6]) and input current limit is updated in IINLIM register (REG00[2:0]). In additon, host can write to REG00[2:0] to change the input current limit.

D+/D– Detection Sets Input Current Limit (bq24297)

The bq24297 contains a D+/D– based input source detection to program the input current limit. The D+/D- detection has three steps: data contact detect (DCD), primary detection, and non-standard adapter detection. When the charging source passes data contact detect, the device would proceed to run primary detection. Otherwise the charger would proceed to run non-standard adapter detection.

bq24296 bq24297 DCD_Data_Contact_Detection_SLUSAW5.gif Figure 12. USB D+/D- Detection

DCD (Data Contact Detection) uses a current source to detect when the D+/D– pins have made contact during an attach event. The protocol for data contact detect is as follows:

  • Detect VBUS present and REG08[2] = 1 (power good)
  • Turn on D+ IDP_SRC and the D– pull-down resistor RDM_DWN for 40 ms
  • If the USB connector is properly attached, the D+ line goes from HIGH to LOW, wait up to 0.5 sec.
  • Turn off IDP_SRC and disconnect RDM_DWN

The primary detection is used to distinguish between USB host (Standard Down Stream Port, or SDP) and different type of charging ports (Charging Down Stream Port, or CDP, and Dedicated Charging Port, or DCP). The protocol for primary detection is as follows:

  • Turn on VDP_SRC on D+ and IDM_SINK on D– for 40 ms
  • If PD is attached to a USB host (SDP), the D– is low. If PD is attached to a charging port (CDP or DCP), the D– is high
  • Turn off VDP_SRC and IDM_SINK

Table 2 shows the input current limit setting after D+/D– detection.

Table 2. bq24297 USB D+/D– Detection

D+/D– DETECTION OTG INPUT CURRENT LIMIT REG08[7:6]
0.5 sec timer expired in DCD (D+/D- floating) Proceed to non-standard adapter detection 00
USB host LOW 100 mA 01
USB host HIGH 500 mA 01
Charging port 3 A 10

When DCD 0.5 sec timer expires, the non-standard adapter detection is used to distinguish three different divider bias conditions on D+/D- pins. When non-standard adapter is detected, the input current limit (REG0[2:0]) is set based on the table shown below and REG08[7:6] is set to 10 (Adapter port). If non-standard adapter is not detected, REG08[7:6] is set to 00 (Unknown) and the input current limit is set in REG0[2:0] to 500 mA by default.

Table 3. bq24297 Non-Standard Adapter Detection

NON-STANDARD
ADAPTER
D+ THRESHOLD D- THRESHOLD INPUT
CURRENT
LIMIT
Divider 1 Vadpt1_lo < VD+ < Vadpt1_hi

For VBUS = 5 V, typical range 2.4 V < VD+ < 3.1 V
VD- < Vadpt1_lo or VD- > Vadpt1_hi

For VBUS = 5 V, typical range VD- < 2.4 V or VD- > 3.1 V
2.0A
Divider 2 Vadpt2_lo < VD+ < Vadpt2_hi

For VBUS = 5 V, typical range 0.85 V < VD+ < 1.5 V
NA 2.0A
Divider 3 VD+< Vadpt3_lo or VD+> Vadpt3_hi

For VBUS = 5 V, typical range VD+ < 2.4 V or VD+ > 3.1 V
Vadpt3_lo < VD- < Vadpt3_hi

For VBUS = 5 V, typical range 2.4 V < VD- < 3.1 V
1A

After D+/D- detection is completed with an input source already plugged in, the input current limit is not changed unless DPDM_EN (REG07[7]) bit is set to force detection.

PSEL/OTG Pins Set Input Current Limit

The bq24296 has PSEL instead of D+/D-. It directly takes the USB PHY device output to decide whether the input is USB host or charging port.

Table 4. bq24296 Input Current Limit Detection

PSEL OTG INPUT CURRENT LIMIT REG08[7:6]
HIGH LOW 100 mA 01
HIGH HIGH 500 mA 01
LOW 3 A 10

HIZ State with 100mA USB Host

In battery charging spec, the good battery threshold is the minimum charge level of a battery to power up the portable device successfully. When the input source is 100-mA USB host, and the battery is above bat-good threshold (VBATGD), the device follows battery charging spec and enters high impedance state (HIZ). In HIZ state, the device is in the lowest quiescent state with REGN LDO and the bias circuits off. The charger device sets REG00[7] to 1, and the VBUS current during HIZ state will be less than 30 µA. The system is supplied by the battery.

Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7] = 0. When the processor host wakes up, it is recommended to first check if the charger is in HIZ state.

In default mode, the charger IC will reset REG00[7] back to 0 when input source is removed. When another source plugs in, the charger IC will run detection again, and update the input current limit.

Force Input Current Limit Detection

While adapter is plugged-in, the host can force the charger device to run input current limit detection by setting REG07[7] = 1 or when watchdog timeout. During the forced detection, the input current limit is set to 100 mA. After the detection is completed, REG07[7] will return to 0 by itself and new input current limit is set based on D+/D- (bq24297) or PSEL/OTG (bq24296).

Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft-start when ramp up the system rail. When the system rail is below 2.2 V, the input current limit is forced to 100mA. After the system rises above 2.2 V, the charger device sets the input current limit set by the lower value between register and ILIM pin.

As a battery charger, the charger deploys a 1.5-MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design.

A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.

In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS.

Boost Mode Operation from Battery

The device supports boost converter operation to deliver power from the battery to other portable devices through USB port. The boost mode output current rating meets the USB On-The-Go 1-A output requirement. The maximum output current is 1.5 A. The boost operation can be enabled if the following conditions are valid:

  1. BAT above BATLOWV threshold (VBATLOWV set by REG04[1])
  2. VBUS less than VBAT + VSLEEP (in sleep mode)
  3. Boost mode operation is enabled (OTG pin HIGH and REG01[5:4] = 10)
  4. Thermistor Temperature is within boost mode temperature monitor threshold unless BHOT[1:0] is set to 11 (REG06[1:0]) to disable this monitor function
  5. After 30ms delay from boost mode enable

In boost mode, the device employs a 1.5-MHz step-up switching regulator. Similar to buck operation, the device switches from PWM operation to PFM operation at light load to improve efficiency.

During boost mode, the status register REG08[7:6] is set to 11, the VBUS output is 5 V and the output current can reach up to 1 A or 1.5 A, selected via I2C (REG01[0]). In addition, the device provides adjustable boost voltage from 4.55 V to 5.5 V by changing BOOSTV bits in REG06[7:4]

Any fault during boost operation, including VBUS over-voltage or over-current, sets the fault register REG09[6] to 1 and an INT is asserted.

Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both.

Narrow VDC Architecture

The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above the minimum system voltage (default 3.5 V).

When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is 150 mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET.

When the battery charging is disabled or terminated, the system is always regulated at 150 mV above the minimum system voltage setting. The status register REG08[0] goes high when the system is in minimum system voltage regulation.

bq24296 bq24297 V_SYS_vs_V_BAT_SLUSAW5.gif Figure 13. V(SYS) vs V(BAT)

Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage.

When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery.

During DPM mode (either VINDPM or IINDPM), the status register REG08[3] will go high.

Figure 14 shows the DPM response with 5-V/1.2-A adapter, 3.2-V battery, 2.0-A charge current and 3.4-V minimum system voltage setting.

bq24296 bq24297 DPM_Response_SLUSBP6.gif Figure 14. DPM Response

Supplement Mode

When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current. shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold.

bq24296 bq24297 BATFET_V_I_lusbu3.gif Figure 15. BATFET V-I Curve

Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 3-A charge current for high capacity tablet battery. The 24-mΩ BATFET improves charging efficiency and minimizes the voltage drop during discharging.

Autonomous Charging Cycle

With battery charging enabled at POR (REG01[5:4] = 01), the charger device complete a charging cycle without host involvement. The device default charging parameters are listed in the following table.

Table 5. Charging Parameter Default Setting

DEFAULT MODE bq24296 / bq24297
Charging voltage 4.208 V
Charging current 2.048 A
Pre-charge current 256 mA
Termination current 256 mA
Temperature profile Hot/Cold
Safety timer 12 hours(1)
See Charging Safety Timer for more information.

A new charge cycle starts when the following conditions are valid:

  • Converter starts
  • Battery charging is enabled by I2C register bit (REG01[5:4]) = 01 and CE is low
  • No thermistor fault on TS
  • No safety timer fault
  • BATFET is not forced to turn off (REG07[5])

The charger device automatically terminates the charging cycle when the charging current is below termination threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below recharge threshold (REG04[0]), the device automatically starts another charging cycle. After the charge done, either toggle CE pin or REG01[5:4] will initiate a new charging cycle.

The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is complete, an INT is asserted to notify the host.

The host can always control the charging operation and optimize the charging parameters by writing to the registers through I2C.

Battery Charging Profile

The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the beginning of a charging cycle, the device checks the battery voltage and applies current.

Table 6. Charging Current Setting

VBAT CHARGING CURRENT REG DEFAULT SETTING REG08[5:4]
VBAT < VSHORT
(Typical 2 V)
100 mA 01
VSHORT ≤ VBAT < VBATLOWV
(Typical 2 V ≤ VBAT < 3 V)
REG03[7:4] 256 mA 01
VBAT ≥ VBATLOWV
(Typical VBAT ≥ 3 V)
REG02[7:2] 2048 mA 10

If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate.

bq24296 bq24297 Battery_Charging_Profile_slusbc1.gif Figure 16. Battery Charging Profile

Thermistor Qualification

The charger device provides a single thermistor input for battery temperature monitor.

Cold/Hot Temperature Window

The device continuously monitors battery temperature by measuring the voltage between the TS pin and ground, typically determined by a negative temperature coefficient thermistor and an external voltage divider. The device compares this voltage against its internal thresholds to determine if charge or boost is allowed.

To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. During the charge cycle the battery temperature must be within the VLTF to VTCO thresholds, else the device suspends charging and waits until the battery temperature is within the VLTF to VHTF range.

For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLDx to VBHOTx thresholds unless boost mode temperature is disabled by setting BHOT bits (REG06[3:2]) to 11. When temperature is outside of the temperature thresholds, the boost mode is suspended and REG08[7:6] bits (VBUS_STAT) are set to 00. Once temperature returns within thresholds, the boost mode is recovered.

bq24296 bq24297 TS_Resistor_Network_SLUSBP6.gif Figure 17. TS Resistor Network

When the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT is asserted to the host. The STAT pin indicates the fault when charging is suspended.

bq24296 bq24297 TS_pin_Therm_Sense_Thresholds_slusbc1.gif Figure 18. TS Pin Thermistor Sense Thresholds in Charge Mode
bq24296 bq24297 TS_Boost2_slusbc1.gif Figure 19. TS Pin Thermistor Sense Thresholds in Boost Mode

Assuming a 103AT NTC thermistor is used on the battery pack Figure 18, the value RT1 and RT2 can be determined by using the following equation:

Equation 1. bq24296 bq24297 Eq1_slusbc1.gif

Select 0°C to 45°C range for Li-ion or Li-polymer battery,
RTHCOLD = 27.28 kΩ
RTHHOT = 4.911 kΩ
RT1 = 5.25 kΩ
RT2 = 31.23 kΩ

Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn back on to engage supplement mode.

When termination occurs, the status register REG08[5:4] is 11, and an INT is asserted to the host. Termination is temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination can be disabled by writing 0 to REG05[7].

Termination When REG02[0] = 1

When REG02[0] is HIGH to reduce the charging current by 80%, the charging current could be less than the termination current. The charger device termination function should be disabled. When the battery is charged to fully capacity, the host disables charging through CE pin or REG01[5:4].

Charging Safety Timer

The device has safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 4 hours when the battery is below batlowv threshold. The user can program fast charge safety timer (default 12 hours) through I2C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C (REG05[3]).

The following actions restart the safety timer after safety timer expires:

  • Toggle the CE pin HIGH to LOW to HIGH (charge enable)
  • Write REG01[5:4] from 00 to 01 (charge enable)
  • Write REG05[3] from 0 to 1 (safety timer enable)

During input voltage/current regulation, thermal regulation, or FORCE_20PCT bit (REG02[0]) is set , the safety timer counting at half clock rate since the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to REG07[6].

Safety Timer Configuration Change

When safety timer value needs to be changed, it is recommended that the timer is disabled first before new configuration is written to REG05[2:1]. The safety timer can be disable by writing 1 to REG05[3]. This ensures the safety timer restart counting after new value is configured.

USB Timer When Charging from USB100mA Source

The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ.

Status Outputs (PG, STAT, and INT)

Power Good Indicator (PG) (bq24296)

In bq24296, PG goes LOW to indicate a good input source when:

  1. VBUS above VBUS_UVLO
  2. VBUS above battery (not in sleep)
  3. VBUS below VACOV threshold
  4. VBUS above VBUS_MIN when IBADSRC current is applied (not a poor source)

Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application diagram shows.

Table 7. STAT Pin State

CHARGING STATE STAT
Charging in progress (including recharge) LOW
Charging complete HIGH
Sleep mode, charge disable HIGH
Charge suspend (Input over-voltage, TS fault, timer fault, input or system over-voltage) blinking at 1Hz

Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT notifies the system on the device operation. The following events will generate a 256-µs INT pulse.

  1. USB/adapter source identified (through PSEL or DPDM detection, and OTG pin)
  2. Good input source detected
    • not in sleep
    • VBUS below VACOV threshold
    • current limit above IBADSRC
  3. Input removed or VBUS above VACOV threshold
  4. Charge Complete
  5. Any FAULT event in REG09

For the first four events, INT pulse is always generated. For the last event, when a fault occurs, the charger device sends out INT and latches the fault state in REG09 until the host reads the fault register. If a prior fault exists, the charger device would not send any INT upon new faults except NTC fault (REG09[2:0]). The NTC fault is not latched and always reports the current thermistor conditions. In order to read the current fault status, the host has to read REG09 two times consecutively. The 1st reads fault register status from the last read and the 2nd reads the current fault register status.

Protections

Input Current Limit on ILIM

For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin. The input maximum current is set by a resistor from ILIM pin to ground as:

Equation 2. bq24296 bq24297 Eq3_slusbp6.gif

The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For example, if the register setting is 111 for 3 A, and ILIM has a 316-Ω resistor to ground for 1.5 A, the input current limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings.

The device regulates ILIM pin at 1 V. If ILIM voltage exceeds 1 V, the device enters input current regulation (Refer to Dynamic Power Path Management section).

The voltage on ILIM pin is proportional to the input current. ILIM pin can be used to monitor the input current following Equation 3:

Equation 3. bq24296 bq24297 Eq4_slusaw5.gif

For example, if ILIM pin sets 2 A, and the ILIM voltage is 0.75 V, the actual input current 1.5 A. If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 1 V. If ILIM pin is short, the input current limit is set by the register.

Thermal Regulation and Thermal Shutdown

During charge operation, the device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]), the device lowers down the charge current. The wide thermal regulation range from 60°C to 120°C allows the user to optimize the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1] goes high.

Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and an INT is asserted to the host.

Voltage and Current Monitoring in Buck Mode

The device closely monitors the input and system voltage, as well as HSFET current for safe buck mode operation.

Input Over-Voltage (ACOV)

The maximum input voltage for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VACOV, the device stops switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An INT is asserted to the host.

System Over-Voltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to clamp the overshoot.

Voltage and Current Monitoring in Boost Mode

The charger device closely monitors the VBUS voltage, as well as LSFET current to ensure safe boost mode operation.

Over-Current Protection

The charger device closely monitors the RBFET (Q1) and LSFET (Q3) current to ensure safe boost mode operation. During over-current condition, the device will operate in hiccup mode for protection. While in hiccup mode cycle, the device turns off RBFET for tOTG_OCP_OFF (32 ms typical) and turns on RBFET for tOTG_OCP_ON (260 us typical) in an attempt to restart. If the over-current condition is removed, the boost converter will maintain the RBFET on state and the VBUS OTG output will operate normally. When over-current condition continues to exist, the device will repeat the hiccup cycle until over-current condition is removed. When over-current condition is detected, the fault register bit BOOST_FAULT (REG09[6]) is set high to indicate fault in boost operation. An INT is asserted to the host.

VBUS Over-Voltage Protection

When an adapter plugs in during boost mode, the VBUS voltage will rise above regulation target. Once the VBUS voltage exceeds VOTG_OVP, the device stops switching and the device exits boost mode. During the over-voltage, the fault register bit BOOST_FAULT (REG09[6]) is set high to indicate fault in boost operation. An INT is asserted to the host.

Battery Protection

Battery Over-Voltage Protection (BATOVP)

The battery over-voltage limit is clamped at VBAT_OVP (4% nominal) above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charge. The fault register REG09[3] goes high and an INT is asserted to the host.

Battery Short Protection

If the battery voltage falls below Vshort (2V typical), the device immediately turns off BATFET to disable the battery charging or supplement mode. 1ms later, the BATFET turns on and charge the battery with 100-mA current. The device does not turn on BATFET to discharge a battery that is below 2.5 V.

System Over-Current Protection

If the system is shorted or exceeds the over-current limit, the device latches off BATFET. DC source insertion on VBUS is required to reset the latch-off condition and turn on BATFET.

Device Functional Modes

Host Mode and Default Mode

The device is a host controlled device, but it can operate in default mode without host management. In default mode, the device can be used as an autonomous charger with no host or with host in sleep.

When the charger is in default mode, REG09[7] is HIGH. When the charger is in host mode, REG09[7] is LOW. After power-on-reset, the device starts in watchdog timer expiration state, or default mode. All the registers are in the default settings. The device keeps charging the battery by default with 12-hour fast charging safety timer. At the end of the 12 hours, the charging is stopped and the buck converter continues to operate to supply system load.

Any write command to device transitions the device from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to REG01[6] before the watchdog timer expires (REG05[5:4]), or disable watchdog timer by setting REG05[5:4] = 00.

When the host changes watchdog timer configuration (REG05[5:4]), it is recommended to first disable watchdog by writing 00 to REG05[5:4] and then change the watchdog to new timer values. This ensures the watchdog timer is restarted after new value is written.

bq24296 bq24297 Watchdog_Timer_Flow_Chart_SLUSAW5.gif Figure 20. Watchdog Timer Flow Chart

Plug in USB100mA Source with Good Battery

When the input source is detected as 100mA USB host, and the battery voltage is above batgood threshold (VBATGD), the charger device enters HIZ state to meet the battery charging spec requirement.

If the charger device is in host mode, it will stay in HIZ state even after the USB100mA source is removed, and the adapter plugs in. During the HIZ state, REG00[7] is set HIGH and the system load is supplied from battery. It is recommended that the processor host always checks if the charger IC is in HIZ state when it wakes up. The host can write REG00[7] to 0 to exit HIZ state.

If the charger is in default mode, when the DC source is removed, the charger device will get out of HIZ state automatically. When the input source plugs in again, the charger IC runs detection on the input source and update the input current limit.

USB Timer When Charging from USB100mA Source

The total charging time in default mode from USB100mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ.

Programming

Serial Interface

The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits).

Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.

Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

bq24296 bq24297 Bit_Transfer_on_the_I2C_Bus_SLUSAW5.gif Figure 21. Bit Transfer on the I2C Bus

START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition.

bq24296 bq24297 START_and_STOP_conditions_SLUSAW5.gif Figure 22. START and STOP Conditions

Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

bq24296 bq24297 Data_Transfer_on_the_I2C_Bus_SLUSAW5.gif Figure 23. Data Transfer on the I2C Bus

Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

bq24296 bq24297 Complete_Data_Transfer_SLUSASW5.gif Figure 24. Complete Data Transfer

Single Read and Write

bq24296 bq24297 Single_Write_SLUSAW5.gif Figure 25. Single Write
bq24296 bq24297 Single_Read_SLUSAW5.gif Figure 26. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG08.

bq24296 bq24297 Multi_Write_SLUSAW5.gif Figure 27. Multi-Write
bq24296 bq24297 Multi_Read_SLUSAW5.gif Figure 28. Multi-Read

The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not support multi-read or multi-write.

REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For example, if there is a TS fault but gets recovered immediately, the host still sees TS fault during the first read. In order to get the fault information at present, the host has to read REG09 for the second time. REG09 does not support multi-read and multi-write.

Register Map

I2C Registers

Address: 6BH. REG00-07 support Read and Write. REG08-0A are Read only.

Input Source Control Register REG00 [reset = 00110xxx, or 3x]

Figure 29. Input Source Control Register REG00 Format
7 6 5 4 3 2 1 0
EN_HIZ VINDPM[3] VINDPM[2] VINDPM[1] VINDPM[0] IINLIM[2] IINLIM[1] IINLIM[0]
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 8. Input Source Control Register REG00 Field Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Bit 7 EN_HIZ R/W 0 0 – Disable, 1 – Enable Default: Disable (0)
Input Voltage Limit
Bit 6 VINDPM[3] R/W 0 640 mV Offset 3.88 V, Range: 3.88 V – 5.08 V
Default: 4.36 V (0110)
Bit 5 VINDPM[2] R/W 1 320 mV
Bit 4 VINDPM[1] R/W 1 160 mV
Bit 3 VINDPM[0] R/W 0 80 mV
Input Current Limit (Actual input current limit is the lower of I2C and ILIM)
Bit 2 IINLIM[2] R/W x 000 – 100 mA, 001 – 150 mA,
010 – 500 mA, 011 – 900 mA, 100 – 1 A, 101 – 1.5 A,
110 – 2 A, 111 – 3A
bq24296
PSEL = Lo : 3 A (111)
PSEL = Hi : 100 mA (000) (OTG pin = Lo) or 500 mA (OTG pin = Hi)
bq24297
Default SDP : 100 mA (000) (OTG pin = Lo) or 500 mA (OTG pin = Hi)
Default DCP/CDP: 3 A (111)
Default Divider 1 and 2 : 2 A (110)
Default Divider 3 : 1 A (100)
Bit 1 IINLIM[1] R/W x
Bit 0 IINLIM[0] R/W x

Power-On Configuration Register REG01 [reset = 00011011, or 0x1B]

Figure 30. Power-On Configuration Register REG01 Format
7 6 5 4 3 2 1 0
Register Reset I2C Watchdog Timer Reset OTG_CONFIG CHG_CONFIG SYS_MIN[2] SYS_MIN[1] SYS_MIN[0] BOOST_LIM
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 9. Power-On Configuration Register REG01 Field Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Bit 7 Register Reset R/W 0 0 – Keep current register setting,
1 – Reset to default
Default: Keep current register setting (0)
Note: Register Reset bit does not reset device to default mode
Bit 6 I2C Watchdog Timer Reset R/W 0 0 – Normal ; 1 – Reset Default: Normal (0)
Note: Consecutive I2C watchdog timer reset requires minimum 20-µs delay
Charger Configuration
Bit 5 OTG_CONFIG R/W 0 0 – OTG Disable; 1 – OTG Enable(1) Default: OTG disable (0)
Note: OTG_CONFIG would over-ride Charge Enable Function in CHG_CONFIG
Bit 4 CHG_CONFIG R/W 1 0- Charge Disable; 1- Charge Enable(1) Default: Charge Battery (1)
Minimum System Voltage Limit
Bit 3 SYS_MIN[2] R/W 1 0.4 V Offset: 3.0 V, Range 3.0 V – 3.7 V
Default: 3.5 V (101)
Bit 2 SYS_MIN[1] R/W 0 0.2 V
Bit 1 SYS_MIN[0] R/W 1 0.1 V
Boost Mode Current Limit
Bit 0 BOOST_LIM R/W 1 0 – 1 A, 1 – 1.5 A Default: 1.5 A (1)
The CHG_CONFIG and OTG_CONFIG bits cannot be set at the same time.

Charge Current Control Register REG02 [reset = 01100000, or 60]

Figure 31. Charge Current Control Register REG02 Format
7 6 5 4 3 2 1 0
ICHG[5] ICHG[4] ICHG[3] ICHG[2] ICHG[1] ICHG[0] BCOLD FORCE_20PCT
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 10. Charge Current Control Register REG02 Field Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Fast Charge Current Limit
Bit 7 ICHG[5] R/W 0 2048 mA Offset: 512 mA
Range: 512 – 3008 mA (000000 – 100111)
Default: 2048 mA (011000)
Note: ICHG higher than 3008mA is not supported
Bit 6 ICHG[4] R/W 1 1024 mA
Bit 5 ICHG[3] R/W 1 512 mA
Bit 4 ICHG[2] R/W 0 256 mA
Bit 3 ICHG[1] R/W 0 128 mA
Bit 2 ICHG[0] R/W 0 64 mA
Bit 1 BCOLD R/W 0 Set Boost Mode temperature monitor threshold voltage to disable boost mode
0 – Vbcold0 (Typ. 76% of REGN or -10°C w/ 103AT thermistor )
1 – Vbcold1 (Typ. 79% of REGN or -20°C w/ 103AT thermistor)
Default: Vbcold0 (0)
Bit 0 FORCE_20PCT R/W 0 0 – ICHG as Fast Charge Current (REG02[7:2]) and IPRECH as Pre-Charge Current (REG03[7:4]) programmed
1 – ICHG as 20% Fast Charge Current (REG02[7:2]) and IPRECH as 50% Pre-Charge Current (REG03[7:4]) programmed
Default: ICHG as Fast Charge Current (REG02[7:2]) and IPRECH as Pre-Charge Current (REG03[7:4]) programmed (0)

Pre-Charge/Termination Current Control Register REG03 [reset = 00010001, or 0x11]

Figure 32. Pre-Charge/Termination Current Control Register REG03 Format
7 6 5 4 3 2 1 0
IPRECHG[3] IPRECHG[2] IPRECHG[1] IPRECHG[0] ITERM[3] ITERM[2] ITERM[1] ITERM[0]
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 11. Pre-Charge/Termination Current Control Register REG03 Field Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Pre-Charge Current Limit
Bit 7 IPRECHG[3] R/W 0 1024 mA Offset: 128 mA,
Range: 128 mA – 2048 mA
Default: 256 mA (0001)
Bit 6 IPRECHG[2] R/W 0 512 mA
Bit 5 IPRECHG[1] R/W 0 256 mA
Bit 4 IPRECHG[0] R/W 1 128 mA
Termination Current Limit
Bit 3 ITERM[3] R/W 0 1024 mA Offset: 128 mA
Range: 128 mA – 2048 mA
Default: 256 mA (0001)
Bit 2 ITERM[2] R/W 0 512 mA
Bit 1 ITERM[1] R/W 0 256 mA
Bit 0 ITERM[0] R/W 1 128 mA

Charge Voltage Control Register REG04 [reset = 10110010, or 0xB2]

Figure 33. Charge Voltage Control Register REG04 Format
7 6 5 4 3 2 1 0
VREG[5] VREG[4] VREG[3] VREG[2] VREG[1] VREG[0] BATLOWV VRECHG
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 12. Charge Voltage Control Register REG04 Field Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Charge Voltage Limit
Bit 7 VREG[5] R/W 1 512 mV Offset: 3.504 V
Range: 3.504 V – 4.400 V
Default: 4.208 V (101100)
Bit 6 VREG[4] R/W 0 256 mV
Bit 5 VREG[3] R/W 1 128 mV
Bit 4 VREG[2] R/W 1 64 mV
Bit 3 VREG[1] R/W 0 32 mV
Bit 2 VREG[0] R/W 0 16 mV
Bit 1 BATLOWV R/W 1 0 – 2.8 V, 1 – 3.0 V Default: 3.0 V (1) (pre-charge to fast charge)
Battery Recharge Threshold (below battery regulation voltage)
Bit 0 VRECHG R/W 0 0 – 100 mV, 1 – 300 mV Default: 100 mV (0)

Charge Termination/Timer Control Register REG05 [reset = 10011010, or 0x9A]

Figure 34. Charge Termination/Timer Control Register REG05 Format
7 6 5 4 3 2 1 0
EN_TERM Reserved WATCHDOG[1] WATCHDOG[0] EN_TIMER CHG_TIMER[1] CHG_TIMER[0] Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 13. Charge Termination/Timer Control Register REG05 Field Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Charging Termination Enable
Bit 7 EN_TERM R/W 1 0 – Disable, 1 – Enable Default: Enable termination (1)
Bit 6 Reserved R/W 0 0 - Reserved
I2C Watchdog Timer Setting
Bit 5 WATCHDOG[1] R/W 0 00 – Disable timer, 01 – 40 s, 10 – 80 s, 11 – 160 s Default: 40 s (01)
Bit 4 WATCHDOG[0] R/W 1
Charging Safety Timer Enable
Bit 3 EN_TIMER R/W 1 0 – Disable, 1 – Enable Default: Enable (1)
Fast Charge Timer Setting
Bit 2 CHG_TIMER[1] R/W 1 00 – 5 hrs, 01 – 8 hrs, 10 – 12 hrs, 11 – 20 hrs Default: 12 hrs (10)
(See Charging Safety Timer for details)
Bit 1 CHG_TIMER[0] R/W 0
Bit 0 Reserved R/W 0 0 - Reserved

Boost Voltage/Thermal Regulation Control Register REG06 [reset = 01110011, or 0x73]

Figure 35. Boost Voltage/Thermal Regulation Control Register REG06 Format
7 6 5 4 3 2 1 0
BOOSTV[3] BOOSTV[2] BOOSTV[1] BOOSTV[0] BHOT[1] BHOT[0] TREG[1] TREG[0]
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 14. Boost Voltage/Thermal Regulation Control Register REG06 Field Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Bit 7 BOOSTV[3] R/W 0 512 mV Offset: 4.55 V
Range: 4.55 V – 5.51 V
Default:4.998 V (0111)
Bit 6 BOOSTV[2] R/W 1 256 mV
Bit 5 BOOSTV[1] R/W 1 128 mV
Bit 4 BOOSTV[0] R/W 1 64 mV
Bit 3 BHOT[1] R/W 0 Set Boost Mode temperature monitor threshold voltage to disable boost mode
Voltage to disable boost mode
00 – Vbhot1 (33% of REGN or 55°C w/ 103AT thermistor)
01 – Vbhot0 (36% of REGN or 60°C w/ 103AT thermistor)
10 – Vbhot2 (30% of REGN or 65°C w/ 103AT thermistor)
11 – Disable boost mode thermal protection.
Default: Vbhot1 (00)
Note: For BHOT[1:0] = 11, boost mode operates without temperature monitor and the NTC_FAULT is generated based on Vbhot1 threshold
Bit 2 BHOT[0] R/W 0
Thermal Regulation Threshold
Bit 1 TREG[1] R/W 1 00 – 60°C, 01 – 80°C, 10 – 100°C, 11 – 120°C Default: 120°C (11)
Bit 0 TREG[0] R/W 1

Misc Operation Control Register REG07 [reset = 01001011, or 4B]

Figure 36. Misc Operation Control Register REG07 Format
7 6 5 4 3 2 1 0
DPDM_EN TMR2X_EN BATFET_Disable Reserved Reserved Reserved INT_MASK[1] INT_MASK[0]
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write

Table 15. Misc Operation Control Register REG07 Field Description

BIT FIELD TYPE RESET DESCRIPTION NOTE
Force DPDM detection
Bit 7 IINDET_EN R/W 0 0 – Not in Input current limit detection;
1 – Force Input current limit detection when VBUS power is presence
Default: Not in Input current limit detection (0), Back to 0 after detection complete
Safety Timer Setting during Input DPM and Thermal Regulation
Bit 6 TMR2X_EN R/W 1 0 – Safety timer not slowed by 2X during input DPM or thermal regulation,
1 – Safety timer slowed by 2X during input DPM or thermal regulation
Default: Safety timer slowed by 2X (1)
Force BATFET Off
Bit 5 BATFET_Disable R/W 0 0 – Allow BATFET (Q4) turn on,
1 – Turn off BATFET (Q4)
Default: Allow BATFET (Q4) turn on(0)
Bit 4 Reserved R/W 0 0 - Reserved
Bit 3 Reserved R/W 1 1 - Reserved
Bit 2 Reserved R/W 0 0 - Reserved
Bit 1 INT_MASK[1] R/W 1 0 – No INT during CHRG_FAULT,
1 – INT on CHRG_FAULT
Default: INT on CHRG_FAULT (1)
Bit 0 INT_MASK[0] R/W 1 0 – No INT during BAT_FAULT,
1 – INT on BAT_FAULT
Default: INT on BAT_FAULT (1)

System Status Register REG08

Figure 37. System Status Register REG08 Format
7 6 5 4 3 2 1 0
VBUS_STAT[1] VBUS_STAT[0] CHRG_STAT[1] CHRG_STAT[0] DPM_STAT PG_STAT THERM_STAT VSYS_STAT
R R R R R R R R
LEGEND: R = Read only

Table 16. System Status Register REG08 Field Description

BIT FIELD TYPE DESCRIPTION
Bit 7 VBUS_STAT[1] R 00 – Unknown (no input, or DPDM detection incomplete), 01 – USB host, 10 – Adapter port, 11 – OTG
Bit 6 VBUS_STAT[0] R
Bit 5 CHRG_STAT[1] R 00 – Not Charging, 01 – Pre-charge (<VBATLOWV), 10 – Fast Charging, 11 – Charge Termination Done
Bit 4 CHRG_STAT[0] R
Bit 3 DPM_STAT R 0 – Not DPM, 1 – VINDPM or IINDPM
Bit 2 PG_STAT R 0 – Not Power Good, 1 – Power Good
Bit 1 THERM_STAT R 0 – Normal, 1 – In Thermal Regulation
Bit 0 VSYS_STAT R 0 – Not in VSYSMIN regulation (BAT > VSYSMIN), 1 – In VSYSMIN regulation (BAT < VSYSMIN)

New Fault Register REG09

Figure 38. New Fault Register REG09 Format
7 6 5 4 3 2 1 0
WATCHDOG_FAULT OTG_FAULT CHRG_FAULT[1] CHRG_FAULT[0] BAT_FAULT Reserved NTC_FAULT[1] NTC_FAULT[0]
R R R R R R R R
LEGEND: R = Read only

Table 17. New Fault Register REG09 Field Description(1)(2)(3)

BIT FIELD TYPE DESCRIPTION
Bit 7 WATCHDOG_FAULT R 0 – Normal, 1- Watchdog timer expiration
Bit 6 OTG_FAULT R 0 – Normal, 1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low (any conditions that cannot start boost function)
Bit 5 CHRG_FAULT[1] R 00 – Normal, 01 – Input fault (OVP or bad source), 10 - Thermal shutdown,
11 – Charge Timer Expiration
Bit 4 CHRG_FAULT[0] R
Bit 3 BAT_FAULT R 0 – Normal, 1 – Battery OVP
Bit 2 Reserved R Reserved – 0
Bit 1 NTC_FAULT[1] R 0-Normal 1–Cold Note: Cold temperature threshold is different based on device operates in buck or boost mode
Bit 0 NTC_FAULT[0] R 0-Normal 1–Hot Note: Hot temperature threshold is different based on device operates in buck or boost mode
REG09 only supports single byte I2C read.
All register bits in REG09 are latched fault. First time read of REG09 clears the previous fault and second read updates fault register to any fault that still presents.
When adapter is unplugged, input fault (bad source) in CHRG_FAULT bits[5:4] is set to 01 once.

Vender / Part / Revision Status Register REG0A

Figure 39. Vender / Part / Revision Status Register REG0A Format
7 6 5 4 3 2 1 0
PN[2] PN[1] PN[0] Reserved Reserved Rev[2] Rev[1] Rev[0]
R R R R R R R R
LEGEND: R = Read only

Table 18. Vender / Part / Revision Status Register REG0A Field Description

BIT FIELD TYPE DESCRIPTION
Bit 7 PN[2] R 001 (bq24296)
011 (bq24297)
Bit 6 PN[1] R
Bit 5 PN[0] R
Bit 4 Reserved R 0 – Reserved
Bit 3 Reserved R 0 – Reserved
Bit 2 Rev[2] R 000
Bit 1 Rev[1] R
Bit 0 Rev[0] R