SLUSDL9A June   2019  – January 2021 BQ25125


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Ship Mode
        1. Ship Mode Entry and Exit
      2. 9.3.2  High Impedance Mode
      3. 9.3.3  Active Battery Only Connected
      4. 9.3.4  Voltage Based Battery Monitor
      5. 9.3.5  Sleep Mode
      6. 9.3.6  Input Voltage Based Dynamic Power Management (VIN(DPM))
      7. 9.3.7  Input Overvoltage Protection and Undervoltage Status Indication
      8. 9.3.8  Battery Charging Process and Charge Profile
      9. 9.3.9  Battery Supplement Mode
      10. 9.3.10 Default Mode
      11. 9.3.11 Termination and Pre-Charge Current Programming by External Components (IPRETERM)
      12. 9.3.12 Input Current Limit Programming by External Components (ILIM)
      13. 9.3.13 Charge Current Programming by External Components (ISET)
      14. 9.3.14 Safety Timer
      15. 9.3.15 External NTC Monitoring (TS)
      16. 9.3.16 Thermal Protection
      17. 9.3.17 Typical Application Power Dissipation
      18. 9.3.18 Status Indicators ( PG and INT)
      19. 9.3.19 Chip Disable ( CD)
      20. 9.3.20 Buck (PWM) Output
      21. 9.3.21 Load Switch / LDO Output and Control
      22. 9.3.22 Manual Reset Timer and Reset Output ( MR and RESET)
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
      2. 9.5.2 F/S Mode Protocol
    6. 9.6 Register Maps
      1. 9.6.1  Status and Ship Mode Control Register
      2. 9.6.2  Faults and Faults Mask Register
      3. 9.6.3  TS Control and Faults Masks Register
      4. 9.6.4  Fast Charge Control Register
      5. 9.6.5  Termination/Pre-Charge Register
      6. 9.6.6  Battery Voltage Control Register
      7. 9.6.7  SYS VOUT Control Register
      8. 9.6.8  Load Switch and LDO Control Register
      9. 9.6.9  Push-button Control Register
      10. 9.6.10 ILIM and Battery UVLO Control Register
      11. 9.6.11 Voltage Based Battery Monitor Register
      12. 9.6.12 VIN_DPM and Timers Register
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Default Settings
        2. Choose the Correct Inductance and Capacitance
        3. Calculations
          1. Program the Fast Charge Current (ISET)
          2. Program the Input Current Limit (ILIM)
          3. Program the Pre-charge/termination Threshold (IPRETERM)
          4. TS Resistors (TS)
      3. 10.2.3 Application Performance Curves
        1. Charger Curves
        2. SYS Output Curves
        3. Load Switch and LDO Curves
        4. LS/LDO Output Curves
        5. Timing Waveforms Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

F/S Mode Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 9-7. All I2C-compatible devices should recognize a start condition.

GUID-ABEA9806-6A5D-4ADC-BC90-B7259F8DE433-low.gifFigure 9-7 Start Stop Condition

The master then generates the SCL pulses, and transmits the address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 9-8). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates and acknowledge (see Figure 9-9) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting the acknowledge, the master knows that communication link with a slave has been established.

GUID-3D2056D6-B420-4DD7-97BC-C77478387852-low.gifFigure 9-8 Bit Transfer on the Serial Interface
GUID-A8D6EF42-D2FD-4F9D-A4AF-4B2F8276A97F-low.gifFigure 9-9 Acknowledge on the I2C Bus

The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on which on is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 9-10). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the STOP condition. Upon the receipt of a STOP condition, all devices know that the bus is released, and wait for a START condition followed by a matching address. If a transaction is terminated prematurely, the master needs to send a STOP condition to prevent the slave I2C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in this section results in 0xFFh being read out.

GUID-A83B7E1F-5DBB-4FE8-88AB-00BF3E7215FB-low.gifFigure 9-10 Bus Protocol