SLUSDL9A June 2019 – January 2021 BQ25125
The device integrates a low Iq load switch which can also be used as a regulated output. The LSCTRL pin can be used to turn the load on or off. Activating LSCTRL continuously holds the switch in the on state so long as there is not a fault. The signal is active HI and has a low threshold making it capable of interfacing with low voltage signals. To limit voltage drop or voltage transients, a small ceramic capacitor must be placed close to VINLS. Due to the body diode of the PMOS switch, it is recommended to have the capacitor on VINLS ten times larger than the output capacitor on LS/LDO.
The output voltage is programmable using the LS_LDO bits in the register. The LS/LDO voltage is calculated using Equation 9.
If a value greater than 3.3 V is written, the setting goes to pass-through mode where LS/LDO = VINLS - V(DROPOUT). Table 9-9 summarizes the control of the LS/LDO output based on the I2C or LSCTRL pin setting:
|I2C LS_LDO_EN||PIN LSCTRL||I2C VLDO > 3.3||LS/LDO OUTPUT|
If the output of the LDO is less than the programmed V(SYS) voltage, connect VINLS to SYS. If the output of the LDO is greater than the programmed VSYS voltage, connect VINLS to PMID.
The current capability of the LDO depends on the VINLS input voltage and the programmed output voltage. The full 100-mA output current for 0.8-V output voltage can be achieved when V(VINLS) > 3.25 V. The full 100-mA output current for 3.3-V output voltage can be achieved when V(VINLS) > 3.6 V.
When the LSLDO output is disabled with LSCTRL or through the register, an internal pull-down discharges the output.